📄 ezregs.lst
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241 sbit ET0 = 0xA8+1;
242 sbit EX1 = 0xA8+2;
243 sbit ET1 = 0xA8+3;
244 sbit ES0 = 0xA8+4;
245 sbit ET2 = 0xA8+5;
246 sbit ES1 = 0xA8+6;
247 sbit EA = 0xA8+7;
248 sfr IP = 0xB8;
249 /* IP */
250 sbit PX0 = 0xB8+0;
251 sbit PT0 = 0xB8+1;
252 sbit PX1 = 0xB8+2;
253 sbit PT1 = 0xB8+3;
254 sbit PS0 = 0xB8+4;
255 sbit PT2 = 0xB8+5;
256 sbit PS1 = 0xB8+6;
257 sfr SCON1 = 0xC0;
258 /* SCON1 */
259 sbit RI1 = 0xC0+0;
260 sbit TI1 = 0xC0+1;
261 sbit RB81 = 0xC0+2;
262 sbit TB81 = 0xC0+3;
263 sbit REN1 = 0xC0+4;
264 sbit SM21 = 0xC0+5;
265 sbit SM11 = 0xC0+6;
266 sbit SM01 = 0xC0+7;
267 sfr SBUF1 = 0xC1;
268 sfr T2CON = 0xC8;
269 /* T2CON */
270 sbit CP_RL2 = 0xC8+0;
271 sbit C_T2 = 0xC8+1;
272 sbit TR2 = 0xC8+2;
273 sbit EXEN2 = 0xC8+3;
274 sbit TCLK = 0xC8+4;
275 sbit RCLK = 0xC8+5;
276 sbit EXF2 = 0xC8+6;
277 sbit TF2 = 0xC8+7;
278 sfr RCAP2L = 0xCA;
279 sfr RCAP2H = 0xCB;
280 sfr TL2 = 0xCC;
281 sfr TH2 = 0xCD;
282 sfr PSW = 0xD0;
283 /* PSW */
284 sbit P = 0xD0+0;
285 sbit FL = 0xD0+1;
286 sbit OV = 0xD0+2;
287 sbit RS0 = 0xD0+3;
288 sbit RS1 = 0xD0+4;
289 sbit F0 = 0xD0+5;
290 sbit AC = 0xD0+6;
291 sbit CY = 0xD0+7;
292 sfr EICON = 0xD8; // Was WDCON in DS80C320; Bit Values differ from Reg320
293 /* EICON */
294 sbit INT6 = 0xD8+3;
295 sbit RESI = 0xD8+4;
296 sbit ERESI = 0xD8+5;
297 sbit SMOD1 = 0xD8+7;
298 sfr ACC = 0xE0;
299 sfr EIE = 0xE8; // EIE Bit Values differ from Reg320
300 /* EIE */
301 sbit EUSB = 0xE8+0;
C51 COMPILER V6.10 EZREGS 06/22/2006 16:09:19 PAGE 6
302 sbit EI2C = 0xE8+1;
303 sbit EIEX4 = 0xE8+2;
304 sbit EIEX5 = 0xE8+3;
305 sbit EIEX6 = 0xE8+4;
306 sfr B = 0xF0;
307 sfr EIP = 0xF8; // EIP Bit Values differ from Reg320
308 /* EIP */
309 sbit PUSB = 0xF8+0;
310 sbit PI2C = 0xF8+1;
311 sbit EIPX4 = 0xF8+2;
312 sbit EIPX5 = 0xF8+3;
313 sbit EIPX6 = 0xF8+4;
314
315 /*-----------------------------------------------------------------------------
316 Bit Masks
317 -----------------------------------------------------------------------------*/
318
319 /* CPU Control & Status Register */
320 #define bmCHIPREV (bmBIT7 | bmBIT6 | bmBIT5 | bmBIT4)
321 #define bmCLK24OE bmBIT1
322 #define bm8052RES bmBIT0
323 /* Port Configuration Registers */
324 /* Port A */
325 #define bmRXD1OUT bmBIT7
326 #define bmRXD0OUT bmBIT6
327 #define bmFRD bmBIT5
328 #define bmFWR bmBIT4
329 #define bmCS bmBIT3
330 #define bmOE bmBIT2
331 #define bmT1OUT bmBIT1
332 #define bmT0OUT bmBIT0
333 /* Port B */
334 #define bmT2OUT bmBIT7
335 #define bmINT6 bmBIT6
336 #define bmINT5 bmBIT5
337 #define bmINT4 bmBIT4
338 #define bmTXD1 bmBIT3
339 #define bmRXD1 bmBIT2
340 #define bmT2EX bmBIT1
341 #define bmT2 bmBIT0
342 /* Port C */
343 #define bmRD bmBIT7
344 #define bmWR bmBIT6
345 #define bmT1 bmBIT5
346 #define bmT0 bmBIT4
347 #define bmINT1 bmBIT3
348 #define bmINT0 bmBIT2
349 #define bmTXD0 bmBIT1
350 #define bmRXD0 bmBIT0
351 /* Isochronous Status & End Point Valid Registers */
352 #define bmEP15 bmBIT7
353 #define bmEP14 bmBIT6
354 #define bmEP13 bmBIT5
355 #define bmEP12 bmBIT4
356 #define bmEP11 bmBIT3
357 #define bmEP10 bmBIT2
358 #define bmEP9 bmBIT1
359 #define bmEP8 bmBIT0
360 /* I2C Control & Status Register */
361 #define bmSTART bmBIT7
362 #define bmSTOP bmBIT6
363 #define bmLASTRD bmBIT5
C51 COMPILER V6.10 EZREGS 06/22/2006 16:09:19 PAGE 7
364 #define bmID (bmBIT4 | bmBIT3)
365 #define bmBERR bmBIT2
366 #define bmACK bmBIT1
367 #define bmDONE bmBIT0
368 /* Interrupt Vector Register */
369 #define bmIV4 bmBIT6
370 #define bmIV3 bmBIT5
371 #define bmIV2 bmBIT4
372 #define bmIV1 bmBIT3
373 #define bmIV0 bmBIT2
374 /* End point Interrupt Request, End Point Interrupt Enable */
375 /* And End Point Valid Registers */
376 #define bmEP7 bmBIT7
377 #define bmEP6 bmBIT6
378 #define bmEP5 bmBIT5
379 #define bmEP4 bmBIT4
380 #define bmEP3 bmBIT3
381 #define bmEP2 bmBIT2
382 #define bmEP1 bmBIT1
383 #define bmEP0 bmBIT0
384 /* Global Interrupt Request & Enable Registers */
385 #define bmIBN bmBIT5
386 #define bmURES bmBIT4
387 #define bmSUSP bmBIT3
388 #define bmSUTOK bmBIT2
389 #define bmSOF bmBIT1
390 #define bmSUDAV bmBIT0
391 /* Global Control */
392 #define bmBREAK bmBIT3
393 #define bmBPPULSE bmBIT2
394 #define bmBPEN bmBIT1
395 #define bmAVEN bmBIT0
396 /* USB Control & Status Register */
397 #define bmRWAKEUP bmBIT7
398 #define bmDISCON bmBIT3
399 #define bmDISCOE bmBIT2
400 #define bmRENUM bmBIT1
401 #define bmSIGRESUME bmBIT0
402 /* End Point 0 Control & Status Register */
403 #define bmOUT bmBIT3
404 #define bmIN bmBIT2
405 #define bmHS bmBIT1
406 #define bmHSSTALL bmBIT0
407 /* End Point Control & Status Registers */
408 #define bmEPSTALL bmBIT0
409 #define bmEPBUSY bmBIT1
410 /* Fast Transfer Register */
411 #define bmFISO bmBIT7
412 #define bmFBLK bmBIT6
413 #define bmRPOL bmBIT5
414 #define bmRMOD1 bmBIT4
415 #define bmRMOD0 bmBIT3
416 #define bmWPOL bmBIT2
417 #define bmWMOD1 bmBIT1
418 #define bmWMOD0 bmBIT0
419 /* Endpoint Pairing Register */
420 #define bmISOSEND0 bmBIT7
421 #define bmPR6OUT bmBIT5
422 #define bmPR4OUT bmBIT4
423 #define bmPR2OUT bmBIT3
424 #define bmPR6IN bmBIT2
425 #define bmPR4IN bmBIT1
C51 COMPILER V6.10 EZREGS 06/22/2006 16:09:19 PAGE 8
426 #define bmPR2IN bmBIT0
427 /* End point control offsets */
428 enum
429 {
430 IN0BUF_ID = 0,
431 IN1BUF_ID,
432 IN2BUF_ID,
433 IN3BUF_ID,
434 IN4BUF_ID,
435 IN5BUF_ID,
436 IN6BUF_ID,
437 IN7BUF_ID,
438 OUT0BUF_ID,
439 OUT1BUF_ID,
440 OUT2BUF_ID,
441 OUT3BUF_ID,
442 OUT4BUF_ID,
443 OUT5BUF_ID,
444 OUT6BUF_ID,
445 OUT7BUF_ID
446 };
447
448 #define EP0CS EPIO[0].cntrl
449 #define IN0BC EPIO[0].bytes
450 #define IN1CS EPIO[1].cntrl
451 #define IN1BC EPIO[1].bytes
452 #define IN2CS EPIO[2].cntrl
453 #define IN2BC EPIO[2].bytes
454 #define IN3CS EPIO[3].cntrl
455 #define IN3BC EPIO[3].bytes
456 #define IN4CS EPIO[4].cntrl
457 #define IN4BC EPIO[4].bytes
458 #define IN5CS EPIO[5].cntrl
459 #define IN5BC EPIO[5].bytes
460 #define IN6CS EPIO[6].cntrl
461 #define IN6BC EPIO[6].bytes
462 #define IN7CS EPIO[7].cntrl
463 #define IN7BC EPIO[7].bytes
464 #define OUT0CS EPIO[8].cntrl
465 #define OUT0BC EPIO[8].bytes
466 #define OUT1CS EPIO[9].cntrl
467 #define OUT1BC EPIO[9].bytes
468 #define OUT2CS EPIO[10].cntrl
469 #define OUT2BC EPIO[10].bytes
470 #define OUT3CS EPIO[11].cntrl
471 #define OUT3BC EPIO[11].bytes
472 #define OUT4CS EPIO[12].cntrl
473 #define OUT4BC EPIO[12].bytes
474 #define OUT5CS EPIO[13].cntrl
475 #define OUT5BC EPIO[13].bytes
476 #define OUT6CS EPIO[14].cntrl
477 #define OUT6BC EPIO[14].bytes
478 #define OUT7CS EPIO[15].cntrl
479 #define OUT7BC EPIO[15].bytes
480
481 /*-----------------------------------------------------------------------------
482 Macros
483 -----------------------------------------------------------------------------*/
484 /* Convert End point ID (d0000eee) to EPIO offset */
485 #define EPID(id) (((~id & 0x80) >> 4) + (id & 0x07))
486
487
C51 COMPILER V6.10 EZREGS 06/22/2006 16:09:19 PAGE 9
488 #endif /* EZREGS_H */
C51 COMPILATION COMPLETE. 0 WARNING(S), 1 ERROR(S)
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