📄 fx2regs.lst
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420 sbit RI1 = 0xC0+0;
421 sbit TI1 = 0xC0+1;
422 sbit RB81 = 0xC0+2;
423 sbit TB81 = 0xC0+3;
424 sbit REN1 = 0xC0+4;
425 sbit SM21 = 0xC0+5;
C51 COMPILER V6.10 FX2REGS 06/22/2006 09:05:31 PAGE 8
426 sbit SM11 = 0xC0+6;
427 sbit SM01 = 0xC0+7;
428 sfr SBUF1 = 0xC1;
429 sfr T2CON = 0xC8;
430 /* T2CON */
431 sbit CP_RL2 = 0xC8+0;
432 sbit C_T2 = 0xC8+1;
433 sbit TR2 = 0xC8+2;
434 sbit EXEN2 = 0xC8+3;
435 sbit TCLK = 0xC8+4;
436 sbit RCLK = 0xC8+5;
437 sbit EXF2 = 0xC8+6;
438 sbit TF2 = 0xC8+7;
439 sfr RCAP2L = 0xCA;
440 sfr RCAP2H = 0xCB;
441 sfr TL2 = 0xCC;
442 sfr TH2 = 0xCD;
443 sfr PSW = 0xD0;
444 /* PSW */
445 sbit P = 0xD0+0;
446 sbit FL = 0xD0+1;
447 sbit OV = 0xD0+2;
448 sbit RS0 = 0xD0+3;
449 sbit RS1 = 0xD0+4;
450 sbit F0 = 0xD0+5;
451 sbit AC = 0xD0+6;
452 sbit CY = 0xD0+7;
453 sfr EICON = 0xD8; // Was WDCON in DS80C320; Bit Values differ from Reg320
454 /* EICON */
455 sbit INT6 = 0xD8+3;
456 sbit RESI = 0xD8+4;
457 sbit ERESI = 0xD8+5;
458 sbit SMOD1 = 0xD8+7;
459 sfr ACC = 0xE0;
460 sfr EIE = 0xE8; // EIE Bit Values differ from Reg320
461 /* EIE */
462 sbit EUSB = 0xE8+0;
463 sbit EI2C = 0xE8+1;
464 sbit EIEX4 = 0xE8+2;
465 sbit EIEX5 = 0xE8+3;
466 sbit EIEX6 = 0xE8+4;
467 sfr B = 0xF0;
468 sfr EIP = 0xF8; // EIP Bit Values differ from Reg320
469 /* EIP */
470 sbit PUSB = 0xF8+0;
471 sbit PI2C = 0xF8+1;
472 sbit EIPX4 = 0xF8+2;
473 sbit EIPX5 = 0xF8+3;
474 sbit EIPX6 = 0xF8+4;
475
476 /*-----------------------------------------------------------------------------
477 Bit Masks
478 -----------------------------------------------------------------------------*/
479
480 /* CPU Control & Status Register (CPUCS) */
481 #define bmPRTCSTB bmBIT5
482 #define bmCLKSPD (bmBIT4 | bmBIT3)
483 #define bmCLKSPD1 bmBIT4
484 #define bmCLKSPD0 bmBIT3
485 #define bmCLKINV bmBIT2
486 #define bmCLKOE bmBIT1
487 #define bm8051RES bmBIT0
C51 COMPILER V6.10 FX2REGS 06/22/2006 09:05:31 PAGE 9
488 /* Port Alternate Configuration Registers */
489 /* Port A (PORTACFG) */
490 #define bmFLAGD bmBIT7
491 #define bmINT1 bmBIT1
492 #define bmINT0 bmBIT0
493 /* Port C (PORTCCFG) */
494 #define bmGPIFA7 bmBIT7
495 #define bmGPIFA6 bmBIT6
496 #define bmGPIFA5 bmBIT5
497 #define bmGPIFA4 bmBIT4
498 #define bmGPIFA3 bmBIT3
499 #define bmGPIFA2 bmBIT2
500 #define bmGPIFA1 bmBIT1
501 #define bmGPIFA0 bmBIT0
502 /* Port E (PORTECFG) */
503 #define bmGPIFA8 bmBIT7
504 #define bmT2EX bmBIT6
505 #define bmINT6 bmBIT5
506 #define bmRXD1OUT bmBIT4
507 #define bmRXD0OUT bmBIT3
508 #define bmT2OUT bmBIT2
509 #define bmT1OUT bmBIT1
510 #define bmT0OUT bmBIT0
511
512 /* I2C Control & Status Register (I2CS) */
513 #define bmSTART bmBIT7
514 #define bmSTOP bmBIT6
515 #define bmLASTRD bmBIT5
516 #define bmID (bmBIT4 | bmBIT3)
517 #define bmBERR bmBIT2
518 #define bmACK bmBIT1
519 #define bmDONE bmBIT0
520 /* I2C Control Register (I2CTL) */
521 #define bmSTOPIE bmBIT1
522 #define bm400KHZ bmBIT0
523 /* Interrupt 2 (USB) Autovector Register (INT2IVEC) */
524 #define bmIV4 bmBIT6
525 #define bmIV3 bmBIT5
526 #define bmIV2 bmBIT4
527 #define bmIV1 bmBIT3
528 #define bmIV0 bmBIT2
529 /* USB Interrupt Request & Enable Registers (USBIE/USBIRQ) */
530 #define bmEP0ACK bmBIT6
531 #define bmHSGRANT bmBIT5
532 #define bmURES bmBIT4
533 #define bmSUSP bmBIT3
534 #define bmSUTOK bmBIT2
535 #define bmSOF bmBIT1
536 #define bmSUDAV bmBIT0
537 /* Breakpoint register (BREAKPT) */
538 #define bmBREAK bmBIT3
539 #define bmBPPULSE bmBIT2
540 #define bmBPEN bmBIT1
541 /* Interrupt 2 & 4 Setup (INTSETUP) */
542 #define bmAV2EN bmBIT3
543 #define INT4IN bmBIT1
544 #define bmAV4EN bmBIT0
545 /* USB Control & Status Register (USBCS) */
546 #define bmHSM bmBIT7
547 #define bmDISCON bmBIT3
548 #define bmNOSYNSOF bmBIT2
549 #define bmRENUM bmBIT1
C51 COMPILER V6.10 FX2REGS 06/22/2006 09:05:31 PAGE 10
550 #define bmSIGRESUME bmBIT0
551 /* Wakeup Control and Status Register (WAKEUPCS) */
552 #define bmWU2 bmBIT7
553 #define bmWU bmBIT6
554 #define bmWU2POL bmBIT5
555 #define bmWUPOL bmBIT4
556 #define bmDPEN bmBIT2
557 #define bmWU2EN bmBIT1
558 #define bmWUEN bmBIT0
559 /* End Point 0 Control & Status Register (EP0CS) */
560 #define bmHSNAK bmBIT7
561 /* End Point 0-1 Control & Status Registers (EP0CS/EP1OUTCS/EP1INCS) */
562 #define bmEPBUSY bmBIT1
563 #define bmEPSTALL bmBIT0
564 /* End Point 2-8 Control & Status Registers (EP2CS/EP4CS/EP6CS/EP8CS) */
565 #define bmNPAK (bmBIT6 | bmBIT5 | bmBIT4)
566 #define bmEPFULL bmBIT3
567 #define bmEPEMPTY bmBIT2
568 /* Endpoint Status (EP2468STAT) SFR bits */
569 #define bmEP8FULL bmBIT7
570 #define bmEP8EMPTY bmBIT6
571 #define bmEP6FULL bmBIT5
572 #define bmEP6EMPTY bmBIT4
573 #define bmEP4FULL bmBIT3
574 #define bmEP4EMPTY bmBIT2
575 #define bmEP2FULL bmBIT1
576 #define bmEP2EMPTY bmBIT0
577 /* SETUP Data Pointer Auto Mode (SUDPTRCTL) */
578 #define bmSDPAUTO bmBIT0
579 /* Endpoint Data Toggle Control (TOGCTL) */
580 #define bmQUERYTOGGLE bmBIT7
581 #define bmSETTOGGLE bmBIT6
582 #define bmRESETTOGGLE bmBIT5
583 #define bmTOGCTLEPMASK bmBIT3 | bmBIT2 | bmBIT1 | bmBIT0
584 /* IBN (In Bulk Nak) enable and request bits (IBNIE/IBNIRQ) */
585 #define bmEP8IBN bmBIT5
586 #define bmEP6IBN bmBIT4
587 #define bmEP4IBN bmBIT3
588 #define bmEP2IBN bmBIT2
589 #define bmEP1IBN bmBIT1
590 #define bmEP0IBN bmBIT0
591
592 /* PING-NAK enable and request bits (NAKIE/NAKIRQ) */
593 #define bmEP8PING bmBIT7
594 #define bmEP6PING bmBIT6
595 #define bmEP4PING bmBIT5
596 #define bmEP2PING bmBIT4
597 #define bmEP1PING bmBIT3
598 #define bmEP0PING bmBIT2
599 #define bmIBN bmBIT0
600
601 /* Interface Configuration bits (IFCONFIG) */
602 #define bmIFCLKSRC bmBIT7
603 #define bm3048MHZ bmBIT6
604 #define bmIFCLKOE bmBIT5
605 #define bmIFCLKPOL bmBIT4
606 #define bmASYNC bmBIT3
607 #define bmGSTATE bmBIT2
608 #define bmIFCFG1 bmBIT1
609 #define bmIFCFG0 bmBIT0
610 #define bmIFCFGMASK (bmIFCFG0 | bmIFCFG1)
611 #define bmIFGPIF bmIFCFG1
C51 COMPILER V6.10 FX2REGS 06/22/2006 09:05:31 PAGE 11
612
613 /* EP 2468 FIFO Configuration bits (EP2FIFOCFG,EP4FIFOCFG,EP6FIFOCFG,EP8FIFOCFG) */
614 #define bmINFM bmBIT6
615 #define bmOEP bmBIT5
616 #define bmAUTOOUT bmBIT4
617 #define bmAUTOIN bmBIT3
618 #define bmZEROLENIN bmBIT2
619 #define bmWORDWIDE bmBIT0
620
621 /* Chip Revision Control Bits (REVCTL) - used to ebable/disable revision specidic
622 features */
623 #define bmNOAUTOARM bmBIT1
624 #define bmSKIPCOMMIT bmBIT0
625
626 /* Fifo Reset bits (FIFORESET) */
627 #define bmNAKALL bmBIT7
628
629 #endif /* FX2REGS_H */
C51 COMPILATION COMPLETE. 0 WARNING(S), 1 ERROR(S)
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