📄 fx2regs.lst
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205 #define EP6GPIFTCL GPIFTCB0 // before REVE silicon (ie. REVB and REVD)
206 #define EP8GPIFTCH GPIFTCB1 // these are here for backwards compatibility
207 #define EP8GPIFTCL GPIFTCB0 // before REVE silicon (ie. REVB and REVD)
208
209 // EXTERN xdata volatile BYTE EP2GPIFTCH _AT_ 0xE6D0; // EP2 GPIF Transaction Count High
210 // EXTERN xdata volatile BYTE EP2GPIFTCL _AT_ 0xE6D1; // EP2 GPIF Transaction Count Low
211 EXTERN xdata volatile BYTE EP2GPIFFLGSEL _AT_ 0xE6D2; // EP2 GPIF Flag select
212 EXTERN xdata volatile BYTE EP2GPIFPFSTOP _AT_ 0xE6D3; // Stop GPIF EP2 transaction on prog. flag
213 EXTERN xdata volatile BYTE EP2GPIFTRIG _AT_ 0xE6D4; // EP2 FIFO Trigger
214 // EXTERN xdata volatile BYTE EP4GPIFTCH _AT_ 0xE6D8; // EP4 GPIF Transaction Count High
215 // EXTERN xdata volatile BYTE EP4GPIFTCL _AT_ 0xE6D9; // EP4 GPIF Transactionr Count Low
216 EXTERN xdata volatile BYTE EP4GPIFFLGSEL _AT_ 0xE6DA; // EP4 GPIF Flag select
217 EXTERN xdata volatile BYTE EP4GPIFPFSTOP _AT_ 0xE6DB; // Stop GPIF EP4 transaction on prog. flag
218 EXTERN xdata volatile BYTE EP4GPIFTRIG _AT_ 0xE6DC; // EP4 FIFO Trigger
219 // EXTERN xdata volatile BYTE EP6GPIFTCH _AT_ 0xE6E0; // EP6 GPIF Transaction Count High
220 // EXTERN xdata volatile BYTE EP6GPIFTCL _AT_ 0xE6E1; // EP6 GPIF Transaction Count Low
221 EXTERN xdata volatile BYTE EP6GPIFFLGSEL _AT_ 0xE6E2; // EP6 GPIF Flag select
222 EXTERN xdata volatile BYTE EP6GPIFPFSTOP _AT_ 0xE6E3; // Stop GPIF EP6 transaction on prog. flag
223 EXTERN xdata volatile BYTE EP6GPIFTRIG _AT_ 0xE6E4; // EP6 FIFO Trigger
224 // EXTERN xdata volatile BYTE EP8GPIFTCH _AT_ 0xE6E8; // EP8 GPIF Transaction Count High
225 // EXTERN xdata volatile BYTE EP8GPIFTCL _AT_ 0xE6E9; // EP8GPIF Transaction Count Low
226 EXTERN xdata volatile BYTE EP8GPIFFLGSEL _AT_ 0xE6EA; // EP8 GPIF Flag select
227 EXTERN xdata volatile BYTE EP8GPIFPFSTOP _AT_ 0xE6EB; // Stop GPIF EP8 transaction on prog. flag
228 EXTERN xdata volatile BYTE EP8GPIFTRIG _AT_ 0xE6EC; // EP8 FIFO Trigger
229 EXTERN xdata volatile BYTE XGPIFSGLDATH _AT_ 0xE6F0; // GPIF Data H (16-bit mode only)
230 EXTERN xdata volatile BYTE XGPIFSGLDATLX _AT_ 0xE6F1; // Read/Write GPIF Data L & trigger transac
231 EXTERN xdata volatile BYTE XGPIFSGLDATLNOX _AT_ 0xE6F2; // Read GPIF Data L, no transac trigger
232 EXTERN xdata volatile BYTE GPIFREADYCFG _AT_ 0xE6F3; // Internal RDY,Sync/Async, RDY5CFG
233 EXTERN xdata volatile BYTE GPIFREADYSTAT _AT_ 0xE6F4; // RDY pin states
234 EXTERN xdata volatile BYTE GPIFABORT _AT_ 0xE6F5; // Abort GPIF cycles
235
236 // UDMA
237
238 EXTERN xdata volatile BYTE FLOWSTATE _AT_ 0xE6C6; //Defines GPIF flow state
239 EXTERN xdata volatile BYTE FLOWLOGIC _AT_ 0xE6C7; //Defines flow/hold decision criteria
C51 COMPILER V6.10 FX2REGS 06/22/2006 09:05:31 PAGE 5
240 EXTERN xdata volatile BYTE FLOWEQ0CTL _AT_ 0xE6C8; //CTL states during active flow state
241 EXTERN xdata volatile BYTE FLOWEQ1CTL _AT_ 0xE6C9; //CTL states during hold flow state
242 EXTERN xdata volatile BYTE FLOWHOLDOFF _AT_ 0xE6CA;
243 EXTERN xdata volatile BYTE FLOWSTB _AT_ 0xE6CB; //CTL/RDY Signal to use as master data strobe
244 EXTERN xdata volatile BYTE FLOWSTBEDGE _AT_ 0xE6CC; //Defines active master strobe edge
245 EXTERN xdata volatile BYTE FLOWSTBHPERIOD _AT_ 0xE6CD; //Half Period of output master strobe
246 EXTERN xdata volatile BYTE GPIFHOLDAMOUNT _AT_ 0xE60C; //Data delay shift
247 EXTERN xdata volatile BYTE UDMACRCH _AT_ 0xE67D; //CRC Upper byte
248 EXTERN xdata volatile BYTE UDMACRCL _AT_ 0xE67E; //CRC Lower byte
249 EXTERN xdata volatile BYTE UDMACRCQUAL _AT_ 0xE67F; //UDMA In only, host terminated use only
250
251
252 // Debug/Test
253
254 EXTERN xdata volatile BYTE DBUG _AT_ 0xE6F8; // Debug
255 EXTERN xdata volatile BYTE TESTCFG _AT_ 0xE6F9; // Test configuration
256 EXTERN xdata volatile BYTE USBTEST _AT_ 0xE6FA; // USB Test Modes
257 EXTERN xdata volatile BYTE CT1 _AT_ 0xE6FB; // Chirp Test--Override
258 EXTERN xdata volatile BYTE CT2 _AT_ 0xE6FC; // Chirp Test--FSM
259 EXTERN xdata volatile BYTE CT3 _AT_ 0xE6FD; // Chirp Test--Control Signals
260 EXTERN xdata volatile BYTE CT4 _AT_ 0xE6FE; // Chirp Test--Inputs
261
262 // Endpoint Buffers
263
264 EXTERN xdata volatile BYTE EP0BUF[64] _AT_ 0xE740; // EP0 IN-OUT buffer
265 EXTERN xdata volatile BYTE EP1OUTBUF[64] _AT_ 0xE780; // EP1-OUT buffer
266 EXTERN xdata volatile BYTE EP1INBUF[64] _AT_ 0xE7C0; // EP1-IN buffer
267 EXTERN xdata volatile BYTE EP2FIFOBUF[1024] _AT_ 0xF000; // 512/1024-byte EP2 buffer (IN or OUT)
268 EXTERN xdata volatile BYTE EP4FIFOBUF[1024] _AT_ 0xF400; // 512 byte EP4 buffer (IN or OUT)
269 EXTERN xdata volatile BYTE EP6FIFOBUF[1024] _AT_ 0xF800; // 512/1024-byte EP6 buffer (IN or OUT)
270 EXTERN xdata volatile BYTE EP8FIFOBUF[1024] _AT_ 0xFC00; // 512 byte EP8 buffer (IN or OUT)
271
272 #undef EXTERN
273 #undef _AT_
274
275 /*-----------------------------------------------------------------------------
276 Special Function Registers (SFRs)
277 The byte registers and bits defined in the following list are based
278 on the Synopsis definition of the 8051 Special Function Registers for EZ-USB.
279 If you modify the register definitions below, please regenerate the file
280 "ezregs.inc" which includes the same basic information for assembly inclusion.
281 -----------------------------------------------------------------------------*/
282
283 sfr IOA = 0x80;
284 sfr SP = 0x81;
285 sfr DPL = 0x82;
286 sfr DPH = 0x83;
287 sfr DPL1 = 0x84;
288 sfr DPH1 = 0x85;
289 sfr DPS = 0x86;
290 /* DPS */
291 sbit SEL = 0x86+0;
292 sfr PCON = 0x87; /* PCON */
293 //sbit IDLE = 0x87+0;
294 //sbit STOP = 0x87+1;
295 //sbit GF0 = 0x87+2;
296 //sbit GF1 = 0x87+3;
297 //sbit SMOD0 = 0x87+7;
298 sfr TCON = 0x88;
299 /* TCON */
300 sbit IT0 = 0x88+0;
301 sbit IE0 = 0x88+1;
C51 COMPILER V6.10 FX2REGS 06/22/2006 09:05:31 PAGE 6
302 sbit IT1 = 0x88+2;
303 sbit IE1 = 0x88+3;
304 sbit TR0 = 0x88+4;
305 sbit TF0 = 0x88+5;
306 sbit TR1 = 0x88+6;
307 sbit TF1 = 0x88+7;
308 sfr TMOD = 0x89;
309 /* TMOD */
310 //sbit M00 = 0x89+0;
311 //sbit M10 = 0x89+1;
312 //sbit CT0 = 0x89+2;
313 //sbit GATE0 = 0x89+3;
314 //sbit M01 = 0x89+4;
315 //sbit M11 = 0x89+5;
316 //sbit CT1 = 0x89+6;
317 //sbit GATE1 = 0x89+7;
318 sfr TL0 = 0x8A;
319 sfr TL1 = 0x8B;
320 sfr TH0 = 0x8C;
321 sfr TH1 = 0x8D;
322 sfr CKCON = 0x8E;
323 /* CKCON */
324 //sbit MD0 = 0x89+0;
325 //sbit MD1 = 0x89+1;
326 //sbit MD2 = 0x89+2;
327 //sbit T0M = 0x89+3;
328 //sbit T1M = 0x89+4;
329 //sbit T2M = 0x89+5;
330 sfr SPC_FNC = 0x8F; // Was WRS in Reg320
331 /* CKCON */
332 //sbit WRS = 0x8F+0;
333 sfr IOB = 0x90;
334 sfr EXIF = 0x91; // EXIF Bit Values differ from Reg320
335 /* EXIF */
336 //sbit USBINT = 0x91+4;
337 //sbit I2CINT = 0x91+5;
338 //sbit IE4 = 0x91+6;
339 //sbit IE5 = 0x91+7;
340 sfr MPAGE = 0x92;
341 sfr SCON0 = 0x98;
342 /* SCON0 */
343 sbit RI = 0x98+0;
344 sbit TI = 0x98+1;
345 sbit RB8 = 0x98+2;
346 sbit TB8 = 0x98+3;
347 sbit REN = 0x98+4;
348 sbit SM2 = 0x98+5;
349 sbit SM1 = 0x98+6;
350 sbit SM0 = 0x98+7;
351 sfr SBUF0 = 0x99;
352
353 sfr APTR1H = 0x9A; // old name
354 sfr APTR1L = 0x9B; // old name
355 sfr AUTOPTR1H = 0x9A;
356 sfr AUTOPTR1L = 0x9B;
357 sfr AUTOPTRH2 = 0x9D;
358 sfr AUTOPTRL2 = 0x9E;
359 sfr IOC = 0xA0;
360 sfr INT2CLR = 0xA1;
361 sfr INT4CLR = 0xA2;
362
363 sfr IE = 0xA8;
C51 COMPILER V6.10 FX2REGS 06/22/2006 09:05:31 PAGE 7
364 /* IE */
365 sbit EX0 = 0xA8+0;
366 sbit ET0 = 0xA8+1;
367 sbit EX1 = 0xA8+2;
368 sbit ET1 = 0xA8+3;
369 sbit ES0 = 0xA8+4;
370 sbit ET2 = 0xA8+5;
371 sbit ES1 = 0xA8+6;
372 sbit EA = 0xA8+7;
373
374 sfr EP2468STAT = 0xAA;
375 /* EP2468STAT */
376 //sbit EP2E = 0xAA+0;
377 //sbit EP2F = 0xAA+1;
378 //sbit EP4E = 0xAA+2;
379 //sbit EP4F = 0xAA+3;
380 //sbit EP6E = 0xAA+4;
381 //sbit EP6F = 0xAA+5;
382 //sbit EP8E = 0xAA+6;
383 //sbit EP8F = 0xAA+7;
384
385 sfr EP24FIFOFLGS = 0xAB;
386 sfr EP68FIFOFLGS = 0xAC;
387 sfr AUTOPTRSETUP = 0xAF;
388 /* AUTOPTRSETUP */
389 sbit EXTACC = 0xAF+0;
390 sbit APTR1FZ = 0xAF+1;
391 sbit APTR2FZ = 0xAF+2;
392
393 sfr IOD = 0xB0;
394 sfr IOE = 0xB1;
395 sfr OEA = 0xB2;
396 sfr OEB = 0xB3;
397 sfr OEC = 0xB4;
398 sfr OED = 0xB5;
399 sfr OEE = 0xB6;
400
401 sfr IP = 0xB8;
402 /* IP */
403 sbit PX0 = 0xB8+0;
404 sbit PT0 = 0xB8+1;
405 sbit PX1 = 0xB8+2;
406 sbit PT1 = 0xB8+3;
407 sbit PS0 = 0xB8+4;
408 sbit PT2 = 0xB8+5;
409 sbit PS1 = 0xB8+6;
410
411 sfr EP01STAT = 0xBA;
412 sfr GPIFTRIG = 0xBB;
413
414 sfr GPIFSGLDATH = 0xBD;
415 sfr GPIFSGLDATLX = 0xBE;
416 sfr GPIFSGLDATLNOX = 0xBF;
417
418 sfr SCON1 = 0xC0;
419 /* SCON1 */
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