📄 gpif.lst
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179 // Wave 3
C51 COMPILER V6.10 GPIF 06/22/2006 16:02:24 PAGE 4
180 /* LenBr */ 0x04, 0x03, 0x02, 0x3F, 0x20, 0x20, 0x20, 0x07,
181 /* Opcode*/ 0x00, 0x02, 0x04, 0x09, 0x00, 0x00, 0x00, 0x00,
182 /* Output*/ 0xFF, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xC0,
183 /* LFun */ 0x12, 0x09, 0x1B, 0x1B, 0x00, 0x2D, 0x36, 0x3F
184 };
185 // END DO NOT EDIT
186
187 // DO NOT EDIT ...
188 const char xdata InitData[7] =
189 {
190 /* Regs */ 0x00,0x00,0x00,0xC0,0x06,0x1B,0x11
191 };
192 // END DO NOT EDIT
193
194 // TO DO: You may add additional code below.
195
196 void GpifInit( void )
197 {
198 1 #ifndef USING_REVD
199 1 BYTE xdata *Source;
200 1 BYTE xdata *Dest;
201 1 BOOL Verified = FALSE;
202 1 #endif
203 1 BYTE i;
204 1
205 1 // 8051 doesn't have access to waveform memories 'til
206 1 // the part is in GPIF mode.
207 1 IFCONFIG = 0xCE; // IFCLKSRC=1 , GPIF executes on internal clk source
208 1 // xMHz=1 , 48MHz internal clk rate
209 1 // IFCLKOE=0 , Don't drive IFCLK pin signal at 48MHz
210 1 // IFCLKPOL=0 , Don't invert IFCLK pin signal from internal clk
211 1 // ASYNC=1 , GPIF samples asynchronous to IFCLK
212 1 // GSTATE=1 , Drive GPIF states out on PORTE[2:0], debug WF
213 1 // IFCFG[1:0]=10, FX2 in GPIF mode
214 1
215 1 // TODO: Configure IFCONFIG appropriately for your application above
216 1 // ...including, manually setting the ASYNC bit
217 1
218 1 GPIFABORT = 0xFF; // abort any waveforms pending
219 1
220 1 // To configure EPx FIFOs, please refer to Slave FIFO TRM Chapter
221 1 //FIFORESET = 0xFF; // reset slave FIFOs
222 1
223 1 // TODO: Configure Slave FIFOs here as per your need.
224 1
225 1 GPIFREADYCFG = InitData[ 0 ];
226 1 GPIFCTLCFG = InitData[ 1 ];
227 1 GPIFIDLECS = InitData[ 2 ];
228 1 GPIFIDLECTL = InitData[ 3 ];
229 1 GPIFWFSELECT = InitData[ 5 ];
230 1 GPIFREADYSTAT = InitData[ 6 ];
231 1
232 1 #ifdef USING_REVD
// TC Expires Not RDY5 Pin feature "bit" polarity swaps from REVB to REVD
// override GPIFTool generated data. (default = enabled)
GPIFREADYCFG |= 0x20; // Don't use TC Expires Not RDY5 Pin feature
// Uncomment the following to use the TC Expires Not RDY5 Pin feature
// GPIFREADYCFG &= ~0x20; // don't use TC Expires Not RDY5 Pin feature
// ...autoptr to waveform memory isn't available in REVB
// REVD dual autopointer feature...
AUTOPTRSETUP = 0x06; // increment both pointers,
C51 COMPILER V6.10 GPIF 06/22/2006 16:02:24 PAGE 5
// ....on-chip access via SFR versions
// Source
APTR1H = MSB( &WaveData );
APTR1L = LSB( &WaveData );
// Destination
AUTOPTRH2 = 0xE4;
AUTOPTRL2 = 0x00;
// Transfer from source to destination
for ( i = 0x00; i < 128; i++ )
{
AUTODAT2 = AUTODAT1;
}
// Now, dual autopointer to scratch ram...
// Source
APTR1H = 0xE4;
APTR1L = 0x00;
// Destination
AUTOPTRH2 = 0xE0;
AUTOPTRL2 = 0x00;
// Transfer from source to Destination
for ( i = 0x00; i < 128; i++ )
{
AUTODAT2 = AUTODAT1;
}
#else
269 1
270 1 // TC Expires Not RDY5 Pin feature "bit" polarity swaps from REVB to REVD
271 1 // override GPIFTool generated data (default = not enabled)
272 1 // Uncomment the following to use the TC Expires Not RDY5 Pin feature
273 1 // GPIFREADYCFG |= 0x20; // use TC Expires Not RDY5 Pin Feature
274 1
275 1 Dest = 0xE47F;
276 1 // implement REVB silicon errata workaround
277 1 // initialize the GPIF waveform RAM to all zeros
278 1 for ( i = 0x00; i < 128; i++ )
279 1 {
280 2 *Dest-- = 0x00;
281 2 }
282 1 Source = &WaveData[ 127 ];
283 1 Dest = 0xE47F;
284 1
285 1 for ( i = 0; i < 128; i++ )
286 1 {
287 2 // only write non-zero registers
288 2 if ( *Source )
289 2 {
290 3 *Dest = *Source;
291 3 }
292 2 Dest--;
293 2 Source--;
294 2 }
295 1
296 1 while ( !Verified )
297 1 {
298 2 Verified = TRUE;
299 2 Source = &WaveData[ 127 ];
300 2 Dest = 0xE47F;
301 2
302 2 for ( i = 0x00; i < 128; i++ )
303 2 {
C51 COMPILER V6.10 GPIF 06/22/2006 16:02:24 PAGE 6
304 3 if ( *Dest != *Source )
305 3 {
306 4 *Dest = *Source;
307 4 Verified = FALSE;
308 4 break;
309 4 }
310 3 else
311 3 {
312 4 Dest--;
313 4 Source--;
314 4 }
315 3 }
316 2 }
317 1 #endif
318 1
319 1
320 1 // Configure GPIF Address pins, output initial value,
321 1 PORTCCFG = 0xFF; // [7:0] as alt. func. GPIFADR[7:0]
322 1 OEC = 0x00; // and as outputs
323 1 PORTECFG |= 0x80; // [8] as alt. func. GPIFADR[8]
324 1 OEC |= 0x80; // and as output
325 1
326 1 // ...OR... tri-state GPIFADR[8:0] pins
327 1 // PORTCCFG = 0x00; // [7:0] as port I/O
328 1 // OEC = 0x00; // and as inputs
329 1 // PORTECFG &= 0x7F; // [8] as port I/O
330 1 // OEC &= 0x7F; // and as input
331 1
332 1 // GPIF address pins update when GPIFADRH/L written
333 1 GPIFADRH = 0x00; // bits[7:1] always 0
334 1 GPIFADRL = 0x00; // point to PERIPHERAL address 0x0000
335 1 // TODO: change GPIF Address pins to meet your needs
336 1
337 1 // Initialize UDMA related registers (default values)
338 1 FLOWSTATE=0x00; //Defines GPIF flow state
339 1 FLOWHOLDOFF=0x00;
340 1 FLOWLOGIC=0x00; //Defines flow/hold decision criteria
341 1 FLOWEQ0CTL=00; //CTL states during active flow state
342 1 FLOWEQ1CTL=0x00; //CTL states during hold flow state
343 1 FLOWSTB=0x20; //CTL/RDY Signal to use as master data strobe
344 1 FLOWSTBEDGE=0x01; //Defines active master strobe edge
345 1 FLOWSTBHPERIOD=0x02; //Half Period of output master strobe
346 1 GPIFHOLDAMOUNT=0x00; //Data delay shift
347 1 UDMACRCQUAL=0x00; //UDMA In only, host terminated use only
348 1 }
MODULE INFORMATION: STATIC OVERLAYABLE
CODE SIZE = 265 ----
CONSTANT SIZE = ---- ----
XDATA SIZE = 135 ----
PDATA SIZE = ---- ----
DATA SIZE = ---- 2
IDATA SIZE = ---- ----
BIT SIZE = ---- 1
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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