📄 gpifburst8a.lst
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234 2 { // ...EP2E=0, when endp FIFO not
235 3 // ...empty, host sent pkt.
236 3 // Since the host sent data, a slave FIFO buffer was available
237 3
238 3 // ... GO on with GPIF write
239 3 if( GPIFTRIG & 0x80 ) // if GPIF done then check slave status
240 3 {
241 4 ledX_rdvar = LED1_OFF; // GPIF is not busy
C51 COMPILER V6.10 GPIFBURST8A 06/27/2006 22:34:28 PAGE 5
242 4 xFIFOTC_OUT = ((EP2BCH<<8) + EP2BCL);
243 4 if( xFIFOTC_OUT ) // pkt is not zerolen, xfr the data
244 4 {
245 5 EP2GPIFTCH = EP2BCH; // Setup transaction count
246 5 EP2GPIFTCL = EP2BCL; // Set EP2GPIFTC = EP2BC
247 5 EP2BCL = 0x00; // AUTOOUT=0, so "pass-on" pkt. to master (GPIF)
248 5 // Skip bit is 0 +> pass on packet to master
249 5 // Once master xfr's OUT pkt, it "auto" (re)arms
250 5
251 5 GPIFTRIG = GPIF_EP2; // Trigger FIFO write transaction(s), using SFR
252 5 // R/W=0, EP[1:0]=FIFO_EpNum for EPx write(s)
253 5 if(xFIFOTC_OUT < 0x0200)// Handle short pkt. to slave, via PA0
254 5 {
255 6 while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 Done bit
256 6 {
257 7 ledX_rdvar = LED1_ON; // GPIF busy
258 7 }
259 6 SHORTPKT = 0; // Signal SHORTPKT to slave (PA0)
260 6 SHORTPKT = 1;
261 6 }
262 5 else // Was max pkt. size
263 5 {
264 6 }
265 5 }
266 4 else // Handle host sending zero length pkt.
267 4 {
268 5 EP2BCL = 0x80; // AUTOOUT=0, so "skip" zerolen pkt.
269 5 // Manually commit packet to the master
270 5 SHORTPKT = 0; // Signal SHORTPKT to slave (PA0)
271 5 SHORTPKT = 1;
272 5 }
273 4 }
274 3 else // GPIF is busy
275 3 {
276 4 ledX_rdvar = LED1_ON; // GPIF is still busy withthe last transfer
277 4 }
278 3
279 3 }
280 2 else // Host is "not" sending data and the
281 2 { // ...slave has taken all data and
282 3 } // ...nothing in the buffer
283 2
284 2
285 2 // Does the slave have data for us...
286 2 if( GPIFTRIG & 0x80 ) // If GPIF done then check slave status
287 2 {
288 3 ledX_rdvar = LED1_OFF; // GPIF is not busy
289 3 if( in_token_event ) // Set via vendor command 0xE0
290 3 {
291 4 ledX_rdvar = LED0_OFF;
292 4 if( !( EP2468STAT & 0x80 ) )// if EP8F=0, buffer is available
293 4 {
294 5 // Trigger FIFO read transaction(s), using SFR
295 5 // R/W=1, EP[1:0]=FIFO_EpNum for EPx read(s)
296 5 GPIFTRIG = GPIFTRIGRD | GPIF_EP8;
297 5 in_token_event = 0;// Clear event flag
298 5 while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 Done bit
299 5 {
300 6 ledX_rdvar = LED1_ON; // GPIF busy
301 6 }
302 5 INPKTEND = 0x08; // AUTOIN=0, so 8051 must "pass-on" pkt to host
303 5 // Short packet => commit to hoist by writting endp
C51 COMPILER V6.10 GPIFBURST8A 06/27/2006 22:34:28 PAGE 6
304 5 } // ....to the INPKTEND register
305 4 else // If EP busy then host is behind (slow) and we
306 4 { // ...still have two buffers containing data
307 5 }
308 4 }
309 3 else // in_token_event not asserted by vendor request
310 3 {
311 4 }
312 3 }
313 2 else // GPIF is busy
314 2 {
315 3 ledX_rdvar = LED1_ON; // GPIF is still busy withthe last transfer
316 3 }
317 2 }
318 1 else
319 1 {
320 2 ledX_rdvar = LED0_OFF; // LED0 is OFF: GPIF not triggered in TD_POll
321 2 }
322 1 }
323
324 BOOL TD_Suspend(void) // Called before the device goes into suspend mode
325 {
326 1 return(TRUE);
327 1 }
328
329 BOOL TD_Resume(void) // Called after the device resumes
330 {
331 1 return(TRUE);
332 1 }
333
334 //-----------------------------------------------------------------------------
335 // Device Request hooks
336 // The following hooks are called by the end point 0 device request parser.
337 //-----------------------------------------------------------------------------
338
339 BOOL DR_GetDescriptor(void)
340 {
341 1 return(TRUE);
342 1 }
343
344 BOOL DR_SetConfiguration(void) // Called when a Set Configuration command is received
345 {
346 1
347 1 Configuration = SETUPDAT[ 2 ];
348 1 return( TRUE ); // Handled by user code
349 1 }
350
351 BOOL DR_GetConfiguration(void) // Called when a Get Configuration command is received
352 {
353 1 EP0BUF[0] = Configuration;
354 1 EP0BCH = 0;
355 1 EP0BCL = 1;
356 1 return(TRUE); // Handled by user code
357 1 }
358
359 BOOL DR_SetInterface(void) // Called when a Set Interface command is received
360 {
361 1 AlternateSetting = SETUPDAT[2];
362 1 return(TRUE); // Handled by user code
363 1 }
364
365 BOOL DR_GetInterface(void) // Called when a Set Interface command is received
C51 COMPILER V6.10 GPIFBURST8A 06/27/2006 22:34:28 PAGE 7
366 {
367 1 EP0BUF[0] = AlternateSetting;
368 1 EP0BCH = 0;
369 1 EP0BCL = 1;
370 1 return(TRUE); // Handled by user code
371 1 }
372
373 BOOL DR_GetStatus(void)
374 {
375 1 return(TRUE);
376 1 }
377
378 BOOL DR_ClearFeature(void)
379 {
380 1 return(TRUE);
381 1 }
382
383 BOOL DR_SetFeature(void)
384 {
385 1 return(TRUE);
386 1 }
387
388
389
390
391 BOOL DR_VendorCmnd( void )
392 {
393 1 switch( SETUPDAT[ 1 ] )
394 1 {
395 2 case VX_A2:
396 2 { // Get status of peripheral function, by doing a GPIF single read transaction
397 3 // using register(s) in XDATA space, dummy read
398 3 while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 Done bit
399 3 {
400 4 ledX_rdvar = LED1_ON; // GPIF Busy
401 4 }
402 3 *EP0BUF = XGPIFSGLDATLX; // trigger GPIF single byte read transaction
403 3 while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 Done bit
404 3 {
405 4 ledX_rdvar = LED1_ON; // GPIF busy
406 4 }
407 3 ledX_rdvar = LED1_OFF; // GPIF not busy anymore
408 3 *EP0BUF = XGPIFSGLDATLNOX; // ...GPIF reads byte from PERIPHERAL
409 3 EP0BCH = 0;
410 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
411 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
412 3 BLINK_LED();
413 3 break;
414 3 }
415 2 case VX_A3:
416 2 { // Tell peripheral we're going into HS mode, by doing a GPIF single write transaction
417 3 while( !( GPIFTRIG & 0x80 ) ) // Poll GPIFTRIG.7 Done bit
418 3 {
419 4 ledX_rdvar = LED1_ON; // GPIF busy
420 4 }
421 3 ledX_rdvar = LED1_OFF; // GPIF not busy anymore
422 3 XGPIFSGLDATLX = 0xA3; // Trigger GPIF
423 3 *EP0BUF = 0xA3;
424 3 EP0BCH = 0;
425 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
426 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
427 3 BLINK_LED();
C51 COMPILER V6.10 GPIFBURST8A 06/27/2006 22:34:28 PAGE 8
428 3 break;
429 3 }
430 2 case VX_A4:
431 2 { // Abort current GPIF transaction...
432 3 GPIFABORT = 0xFF;
433 3 *EP0BUF = 0xA4;
434 3 EP0BCH = 0;
435 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
436 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
437 3 BLINK_LED();
438 3 break;
439 3 }
440 2 case VX_A6:
441 2 { // Turn debug LED[3:0] off...
442 3 ledX_rdvar = LED0_OFF;
443 3 ledX_rdvar = LED1_OFF;
444 3 ledX_rdvar = LED2_OFF;
445 3 ledX_rdvar = LED3_OFF;
446 3 *EP0BUF = 0xA6;
447 3 EP0BCH = 0;
448 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
449 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
450 3 BLINK_LED();
451 3 break;
452 3 }
453 2 case VX_A7:
454 2 { // Setup peripheral for high speed FIFO xfr(s), TC=8 bytes
455 3 EP8GPIFTCH = 0x00; // setup transaction count
456 3 EP8GPIFTCL = 0x08; // set EP8GPIFTC = 8
457 3 *EP0BUF = 0xA7;
458 3 EP0BCH = 0;
459 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
460 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
461 3 BLINK_LED();
462 3 break;
463 3 }
464 2 case VX_A8:
465 2 { // Do a FIFO Rd transaction w/TC=8 into EP8
466 3 if( !( EP2468STAT & 0x80 ) )
467 3 { // EP8FF=0, when buffer is available...
468 4 // trigger FIFO read transaction(s), using SFR
469 4 while( !( GPIFTRIG & 0x80 ) ) // Poll GPIFTRIG.7 Done bit
470 4 {
471 5 ledX_rdvar = LED1_ON; // GPIF busy
472 5 }
473 4 ledX_rdvar = LED1_OFF; // GPIF not busy anymore
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