📄 gpifburst8a.lst
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C51 COMPILER V6.10 GPIFBURST8A 06/27/2006 22:34:28 PAGE 1
C51 COMPILER V6.10, COMPILATION OF MODULE GPIFBURST8A
OBJECT MODULE PLACED IN .\gpifburst8a.OBJ
COMPILER INVOKED BY: C:\Keil\C51\BIN\C51.EXE .\gpifburst8a.c OPTIMIZE(6,SPEED) DEBUG OBJECTEXTEND
stmt level source
1 #pragma NOIV // Do not generate interrupt vectors
2 //-----------------------------------------------------------------------------
3 // File: gpifburst8a.c v0.3 - (implemented for rev B silicon only)
4 // Contents: Hooks required to implement USB peripheral function.
5 //
6 // Copyright (c) 1997 AnchorChips, Inc. All rights reserved
7 //-----------------------------------------------------------------------------
8 #include "fx2.h"
9 #include "fx2regs.h"
10 #include "fx2sdly.h" // SYNCDELAY macro
11
12
13 extern BOOL GotSUD; // Received setup data flag
14 extern BOOL Sleep;
15 extern BOOL Rwuen;
16 extern BOOL Selfpwr;
17
18 BYTE Configuration; // Current configuration
19 BYTE AlternateSetting; // Alternate settings
20
21 // EZUSB FX2 PORTA i/o...
22 sbit SHORTPKT = IOA ^ 0;
23 sbit PA1 = IOA ^ 1;
24 sbit PA2 = IOA ^ 2;
25 sbit PA3 = IOA ^ 3;
26 sbit PA4 = IOA ^ 4;
27 sbit PA5 = IOA ^ 5;
28 sbit PA6 = IOA ^ 6;
29 sbit PA7 = IOA ^ 7;
30
31 // EZUSB FX2 PORTD = FD[15:8], when IFCFG[1:0]=10 and WORDWIDE=1
32 sbit PD0 = IOD ^ 0;
33 sbit PD1 = IOD ^ 1;
34 sbit PD2 = IOD ^ 2;
35 sbit PD3 = IOD ^ 3;
36 sbit PD4 = IOD ^ 4;
37 sbit PD5 = IOD ^ 5;
38 sbit PD6 = IOD ^ 6;
39 sbit PD7 = IOD ^ 7;
40
41 // EZUSB FX2 PORTE is not bit-addressable...
42 // PORTE.7 - GPIFADR[8], when IFCFG[1:0]=10 and PORTECFG.7=1
43 // Debug LEDs: accessed via movx reads only ( through CPLD )
44 xdata volatile const BYTE LED0_ON _at_ 0x8000; // GPIF event triggered in TD_Poll
45 xdata volatile const BYTE LED0_OFF _at_ 0x8100; // GPIF Event triggered by vendor request
46 xdata volatile const BYTE LED1_ON _at_ 0x9000; // Vendor request is copmpleted succesfully
47 xdata volatile const BYTE LED1_OFF _at_ 0x9100;
48 xdata volatile const BYTE LED2_ON _at_ 0xA000; // Empty buffer
49 xdata volatile const BYTE LED2_OFF _at_ 0xA100;
50 xdata volatile const BYTE LED3_ON _at_ 0xB000;
51 xdata volatile const BYTE LED3_OFF _at_ 0xB100;
52
53 // NOTE: The default monitor loads at 0xC000
54
55 BYTE ledX_rdvar = 0x00; // Use this global variable when (de)asserting debug LEDs
C51 COMPILER V6.10 GPIFBURST8A 06/27/2006 22:34:28 PAGE 2
56 BOOL xfrvia_TD_Poll = 0; // Event flg for execution in TD_Poll( );
57 BOOL in_token_event = 0; // Event flg for GPIF FIFO Read trigger
58
59 // Core uses bRequest value 0xA0 for Anchor downloads/uploads...
60 // Cypress Semiconductor reserves bRequest values 0xA1 through 0xAF...
61 // Your implementation should not use the above bRequest values...
62 // Also, previous fw.c versions trap all bRequest values 0x00 through 0x0F...
63 //
64 // bRequest value: SETUPDAT[1]
65 // standard, 0x00 through 0x0F
66 //
67 // bmRequest value: SETUPDAT[0]
68 // standard, 0x80 IN Token
69 // vendor, 0xC0 IN Token
70 // class, 0xA0 IN Token
71 // standard, 0x00 OUT Token
72 // vendor, 0x40 OUT Token
73 // class, 0x60 OUT Token
74
75 #define VX_A2 0xA2 // testing, GPIF single byte read waveform
76 #define VX_A3 0xA3 // testing, GPIF single byte write waveform
77 #define VX_A4 0xA4 // testing, GPIFABORT
78 #define VX_A6 0xA6 // turn debug LED[3:0] off...
79 #define VX_A7 0xA7 // setup peripheral for high speed FIFO xfr(s), TC=8
80 #define VX_A8 0xA8 // do a FIFO Rd transaction w/TC=8 into EP8
81 #define VX_A9 0xA9 // do a FIFO Wr transaction w/TC=BC from EP2
82 #define VX_AA 0xAA // manually commit IN data to host... EP8BC=FIFOBC
83 #define VX_AB 0xAB // manually commit OUT data to master...
84 #define VX_AC 0xAC // manually commit IN data to host... INPKTEND
85 #define VX_AD 0xAD // setup GPIF FIFO Reads w/TC=8
86 #define VX_AE 0xAE // return status of GPIF
87 #define VX_AF 0xAF // comitt one zerolen IN pkts
88
89 #define VX_B1 0xB1 // examine flag status, XDATA - EP8FIFOFLGS
90 #define VX_B2 0xB2 // examine flag status, XDATA - EP8CS
91 #define VX_B3 0xB3 // examine flag status, SFR - EP68FIFOFLGS
92 #define VX_B4 0xB4 // examine ep8bch
93 #define VX_B5 0xB5 // examine ep8bcl
94 #define VX_B6 0xB6 // examine ep8fifobcl
95 #define VX_B7 0xB7 // examine ep8fifobcl
96
97 #define VX_C1 0xC1 // examine flag status, XDATA - EP2FIFOFLGS
98 #define VX_C2 0xC2 // examine flag status, XDATA - EP2CS
99 #define VX_C3 0xC3 // examine flag status, SFR - EP24FIFOFLGS
100 #define VX_C4 0xC4 // examine ep2bch
101 #define VX_C5 0xC5 // examine ep2bcl
102 #define VX_C6 0xC6 // examine ep2fifobcl
103 #define VX_C7 0xC7 // examine ep2fifobcl
104
105 #define VX_D1 0xD1 // let TD_Poll( ); firmware handle data xfr's...
106 #define VX_D2 0xD2 // handle data xfr's via vendor specific cmds...
107
108 #define VX_E0 0xE0 // set GPIF FIFO Read event flag
109
110
111 // Protocols from gpif.c
112 void GpifInit( void );
113
114 // Some #defines from gpif.c, typically be in a common header file
115 #define GPIF_FLGSELPF 0
116 #define GPIF_FLGSELEF 1
117 #define GPIF_FLGSELFF 2
C51 COMPILER V6.10 GPIFBURST8A 06/27/2006 22:34:28 PAGE 3
118
119 #define GPIFTRIGWR 0
120 #define GPIFTRIGRD 4
121
122 #define GPIF_EP2 0
123 #define GPIF_EP4 1
124 #define GPIF_EP6 2
125 #define GPIF_EP8 3
126
127
128 //#define USING_REVD // Select silicon revision (comment for REVB)
129
130 //-----------------------------------------------------------------------------
131 // Task Dispatcher hooks
132 // The following hooks are called by the task dispatcher.
133 //-----------------------------------------------------------------------------
134
135 void BLINK_LED(void)
136 {
137 1 ledX_rdvar = LED2_ON; // LED1 is ON => vend request completed
138 1 EZUSB_Delay(1000); // Wait for 1 second
139 1 ledX_rdvar = LED2_OFF; // LED1 is off => reset LED1
140 1 }
141
142
143 void TD_Init( void )
144 { // Called once at startup
145 1
146 1 #ifdef USING_REVD
// 8051 sets CLKSPD...
CPUCS = 0x10; // CLKSPD[1:0]=10, for 48MHz operation
// ...default 12MHz...
// don't drive CLKOUT (CLKOE=0=>Not Driving CLKOUT)
#else
152 1 // FX2 REVB silicon...
153 1 // CLKSPD[1:0] core sets via serial eeprom config byte values
154 1 // ...default 48MHz...
155 1 // CLKOE bit has swapped bit setting...
156 1 CPUCS = 0x02; // don't drive CLKOUT (CLKOE=1=>Not Driving CLKOUT)
157 1 #endif
158 1
159 1 GpifInit( ); // Configure GPIF from GPIFTool generated waveform data
160 1
161 1 #ifdef USING_REVD
SYNCDELAY;
FIFORESET = 0x80; // activate NAK-ALL to avoid race conditions
SYNCDELAY; // see TRM section 15.14
FIFORESET = 0x02; // reset, FIFO 2
SYNCDELAY; //
FIFORESET = 0x08; // reset, FIFO 8
SYNCDELAY; //
FIFORESET = 0x00; // deactivate NAK-ALL
#else
171 1 SYNCDELAY;
172 1 FIFORESET = 0xFF; // reset ALL slave fifo's (2,4,6,8)
173 1
174 1 #endif
175 1
176 1 // default: all endpoints have their VALID bit set
177 1 // default: TYPE1 = 1 and TYPE0 = 0 --> BULK
178 1 // default: EP2 and EP4 DIR bits are 0 (OUT direction)
179 1 // default: EP6 and EP8 DIR bits are 1 (IN direction)
C51 COMPILER V6.10 GPIFBURST8A 06/27/2006 22:34:28 PAGE 4
180 1 // default: EP2, EP4, EP6, and EP8 are double buffered
181 1 SYNCDELAY;
182 1 EP2FIFOCFG = 0x04;
183 1 // NA=0 , NULL bit field
184 1 // INFM1=0 , don't IN full minus 1 status flag
185 1 // OEP1=0 , don't OUT empty plus 1 status flag, not used for IN endp
186 1 // AUTOOUT=0 , use manual mode, 8051 is responsible for commit pkt(s).
187 1 // AUTOIN=0 , not applicable for OUT endp
188 1 // ZEROLENIN=1 , send zerolen pkt on PKTEND
189 1 // NA=0 , NULL bit field
190 1 // WORDWIDE=0 , use 8-bit databus
191 1 // The EPx WORDWIDE bits must to be set to configure
192 1 // ...PORTD as FD[15:8] for single transactions if "any"
193 1 // ...of the WORDWIDE bits are set, then PORTD is FD[15:8]
194 1 SYNCDELAY;
195 1 EP8FIFOCFG = 0x04;
196 1
197 1 // Since we're in manual mode, we need to initially arm out pkt(s)
198 1 // Out endpoints do not come up armed. Need to be armed
199 1 // Since the defaults are double buffered we must write
200 1 // ...dummy byte counts twice
201 1 SYNCDELAY;
202 1 EP2BCL = 0x80; // Commit buffer, 1x - w/skip=1
203 1 SYNCDELAY;
204 1 EP2BCL = 0x80; // Commit buffer, 2x - w/skip=1
205 1
206 1 EP8AUTOINLENH = 0x02; // When AUTOIN=1, core commits IN data
207 1 EP8AUTOINLENL = 0x00; // ...when EPxAUTOINLEN value is met
208 1
209 1 PORTACFG = 0x00; // PORTA as I/O pins
210 1 OEA = 0xFF; // Set PORTA as outputs
211 1
212 1 GPIFADRH = 0x00; // Setup initial gpif address
213 1 GPIFADRL = 0x00; // ...outputs.
214 1
215 1 EP8GPIFTCH = 0x00; // Setup initial transaction count
216 1 EP8GPIFTCL = 0x08; // EP8GPIFTC = 8 bytes
217 1
218 1 // Turn debug LED[3:0] off (default)
219 1 ledX_rdvar = LED0_OFF;
220 1 ledX_rdvar = LED1_OFF;
221 1 ledX_rdvar = LED2_OFF;
222 1 ledX_rdvar = LED3_OFF;
223 1 }
224
225
226 void TD_Poll( void )
227 { // Called repeatedly while the device is idle
228 1 static WORD xFIFOTC_OUT = 0x0000;
229 1
230 1 if( xfrvia_TD_Poll ) // Set to TRUE vendor command 0xD1...
231 1 {
232 2 ledX_rdvar = LED0_ON; // LED0 is ON: GPIF triggered in TD_POll
233 2 if( !( EP2468STAT & 0x01 ) ) // Is the host busy sending data
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