reg167.h

opentcp-8052-1-0-4-1-src,包含了常用的网络协议

sbit  CSREN3   = BUSCON3^14;
sbit  CSWEN3   = BUSCON3^15;
sbit  RWDC4    = BUSCON4^4;
sbit  MTTC4    = BUSCON4^5;
sbit  ALECTL4  = BUSCON4^9;
sbit  BUSACT4  = BUSCON4^10;
sbit  RDYEN4   = BUSCON4^12;
sbit  CSREN4   = BUSCON4^14;
sbit  CSWEN4   = BUSCON4^15;
sbit  ILLBUS   = TFR^0;
sbit  ILLINA   = TFR^1;
sbit  ILLOPA   = TFR^2;
sbit  PRTFLT   = TFR^3;
sbit  UNDOPC   = TFR^7;
sbit  STKUF    = TFR^13;
sbit  STKOF    = TFR^14;
sbit  NMI      = TFR^15;

sfr   EXICON   = 0xF1C0;

sfr   ISNC     = 0xF1DE;
sbit  RTCIR    = ISNC^0;
sbit  RTCIE    = ISNC^1;
sbit  PLLIR    = ISNC^2;
sbit  PLLIE    = ISNC^3;


/* PEC */
sfr   PECC0    = 0xFEC0;
sfr   PECC1    = 0xFEC2;
sfr   PECC2    = 0xFEC4;
sfr   PECC3    = 0xFEC6;
sfr   PECC4    = 0xFEC8;
sfr   PECC5    = 0xFECA;
sfr   PECC6    = 0xFECC;
sfr   PECC7    = 0xFECE;

#define  SRCP0 (*((unsigned int volatile sdata *) 0xFCE0))
#define  DSTP0 (*((unsigned int volatile sdata *) 0xFCE2))
#define  SRCP1 (*((unsigned int volatile sdata *) 0xFCE4))
#define  DSTP1 (*((unsigned int volatile sdata *) 0xFCE6))
#define  SRCP2 (*((unsigned int volatile sdata *) 0xFCE8))
#define  DSTP2 (*((unsigned int volatile sdata *) 0xFCEA))
#define  SRCP3 (*((unsigned int volatile sdata *) 0xFCEC))
#define  DSTP3 (*((unsigned int volatile sdata *) 0xFCEE))
#define  SRCP4 (*((unsigned int volatile sdata *) 0xFCF0))
#define  DSTP4 (*((unsigned int volatile sdata *) 0xFCF2))
#define  SRCP5 (*((unsigned int volatile sdata *) 0xFCF4))
#define  DSTP5 (*((unsigned int volatile sdata *) 0xFCF6))
#define  SRCP6 (*((unsigned int volatile sdata *) 0xFCF8))
#define  DSTP6 (*((unsigned int volatile sdata *) 0xFCFA))
#define  SRCP7 (*((unsigned int volatile sdata *) 0xFCFC))
#define  DSTP7 (*((unsigned int volatile sdata *) 0xFCFE))

/* I/O Ports */
sfr   DP0L     = 0xF100;
sfr   DP0H     = 0xF102;
sfr   DP1L     = 0xF104;
sfr   DP1H     = 0xF106;
sfr   DP2      = 0xFFC2;
sfr   DP3      = 0xFFC6;
sfr   DP4      = 0xFFCA;
sfr   DP6      = 0xFFCE;
sfr   DP7      = 0xFFD2;
sfr   DP8      = 0xFFD6;
sfr   P0L      = 0xFF00;
sfr   P0H      = 0xFF02;
sfr   P1L      = 0xFF04;
sfr   P1H      = 0xFF06;
sfr   P2       = 0xFFC0;
sfr   P3       = 0xFFC4;
sfr   P4       = 0xFFC8;
sfr   P5       = 0xFFA2;
sfr   P6       = 0xFFCC;
sfr   P7       = 0xFFD0;
sfr   P8       = 0xFFD4;
sfr   ODP2     = 0xF1C2;
sfr   ODP3     = 0xF1C6;
sfr   ODP6     = 0xF1CE;
sfr   ODP7     = 0xF1D2;
sfr   ODP8     = 0xF1D6;
sfr   RP0H     = 0xF108;

/* Serial Interface */
sfr   S0BG     = 0xFEB4;
sfr   S0CON    = 0xFFB0;
sfr   S0EIC    = 0xFF70;
sfr   S0RBUF   = 0xFEB2;
sfr   S0RIC    = 0xFF6E;
sfr   S0TBUF   = 0xFEB0;
sfr   S0TIC    = 0xFF6C;
sfr   S0TBIC   = 0xF19C;
sbit  S0STP    = S0CON^3;
sbit  S0REN    = S0CON^4;
sbit  S0PEN    = S0CON^5;
sbit  S0FEN    = S0CON^6;
sbit  S0OEN    = S0CON^7;
sbit  S0PE     = S0CON^8;
sbit  S0FE     = S0CON^9;
sbit  S0OE     = S0CON^10;
sbit  S0ODD    = S0CON^12;
sbit  S0BRS    = S0CON^13;
sbit  S0LB     = S0CON^14;
sbit  S0R      = S0CON^15;
sbit  S0TIE    = S0TIC^6;
sbit  S0TIR    = S0TIC^7;
sbit  S0TBIE   = S0TBIC^6;
sbit  S0TBIR   = S0TBIC^7;
sbit  S0RIE    = S0RIC^6;
sbit  S0RIR    = S0RIC^7;
sbit  S0EIE    = S0EIC^6;
sbit  S0EIR    = S0EIC^7;

sfr   SSCTIC   = 0xFF72;
sfr   SSCRIC   = 0xFF74;
sfr   SSCEIC   = 0xFF76;
sfr   SSCTB    = 0xF0B0;
sfr   SSCRB    = 0xF0B2;
sfr   SSCBR    = 0xF0B4;
sfr   SSCCON   = 0xFFB2;
sbit  SSCHB    = SSCCON^4;
sbit  SSCPH    = SSCCON^5;
sbit  SSCPO    = SSCCON^6;
sbit  SSCTE    = SSCCON^8;
sbit  SSCTEN   = SSCCON^8;
sbit  SSCRE    = SSCCON^9;
sbit  SSCREN   = SSCCON^9;
sbit  SSCPE    = SSCCON^10;
sbit  SSCPEN   = SSCCON^10;
sbit  SSCBE    = SSCCON^11;
sbit  SSCBEN   = SSCCON^11;
sbit  SSCBSY   = SSCCON^12;
sbit  SSCMS    = SSCCON^14;
sbit  SSCEN    = SSCCON^15;
sbit  SSCTIR   = SSCTIC^7;
sbit  SSCTIE   = SSCTIC^6;
sbit  SSCRIR   = SSCRIC^7;
sbit  SSCRIE   = SSCRIC^6;
sbit  SSCEIR   = SSCEIC^7;
sbit  SSCEIE   = SSCEIC^6;

/* GPT1, GPT2 */
sfr   CAPREL   = 0xFE4A;
sfr   CRIC     = 0xFF6A;
sfr   T2       = 0xFE40;
sfr   T2CON    = 0xFF40;
sfr   T2IC     = 0xFF60;
sfr   T3       = 0xFE42;
sfr   T3CON    = 0xFF42;
sfr   T3IC     = 0xFF62;
sfr   T4       = 0xFE44;
sfr   T4CON    = 0xFF44;
sfr   T4IC     = 0xFF64;
sfr   T5       = 0xFE46;
sfr   T5CON    = 0xFF46;
sfr   T5IC     = 0xFF66;
sfr   T6       = 0xFE48;
sfr   T6CON    = 0xFF48;
sfr   T6IC     = 0xFF68;
sfr   WDT      = 0xFEAE;
sfr   WDTCON   = 0xFFAE;
sbit  CRIE     = CRIC^6;
sbit  CRIR     = CRIC^7;
sbit  T2R      = T2CON^6;
sbit  T2UD     = T2CON^7;
sbit  T2UDE    = T2CON^8;
sbit  T2IE     = T2IC^6;
sbit  T2IR     = T2IC^7;
sbit  T3R      = T3CON^6;
sbit  T3UD     = T3CON^7;
sbit  T3UDE    = T3CON^8;
sbit  T3OE     = T3CON^9;
sbit  T3OTL    = T3CON^10;
sbit  T3IE     = T3IC^6;
sbit  T3IR     = T3IC^7;
sbit  T4R      = T4CON^6;
sbit  T4UD     = T4CON^7;
sbit  T4UDE    = T4CON^8;
sbit  T4IE     = T4IC^6;
sbit  T4IR     = T4IC^7;
sbit  T5R      = T5CON^6;
sbit  T5UD     = T5CON^7;
sbit  T5UDE    = T5CON^8;
sbit  T5CLR    = T5CON^14;
sbit  T5SC     = T5CON^15;
sbit  T5IE     = T5IC^6;
sbit  T5IR     = T5IC^7;
sbit  T6R      = T6CON^6;
sbit  T6UD     = T6CON^7;
sbit  T6UDE    = T6CON^8;
sbit  T6OE     = T6CON^9;
sbit  T6OTL    = T6CON^10;
sbit  T6SR     = T6CON^15;
sbit  T6IE     = T6IC^6;
sbit  T6IR     = T6IC^7;
sbit  T0IN     = P3^0;
sbit  T2IN     = P3^7;
sbit  T3IN     = P3^6;
sbit  T4IN     = P3^5;
sbit  T5IN     = P5^13;
sbit  T6IN     = P5^12;
sbit  T2EUD    = P5^15;
sbit  T3EUD    = P3^4;
sbit  T4EUD    = P5^14;
sbit  T5EUD    = P5^11;
sbit  T6EUD    = P5^10;
sbit  T3OUT    = P3^3;
sbit  CAPIN    = P3^2;
sbit  T6OUT    = P3^1;
sbit	WDTIN    = WDTCON^0;
sbit	WDTR     = WDTCON^1;
sbit	SWR      = WDTCON^2;
sbit	SHWR     = WDTCON^3;
sbit	LHWR     = WDTCON^4;
sbit	PONR     = WDTCON^5;
sbit	WDTPRE   = WDTCON^7;

/* PWM Module */
sfr   PWMCON0  = 0xFF30;
sfr   PWMCON1  = 0xFF32;
sfr   PW0      = 0xFE30;
sfr   PW1      = 0xFE32;
sfr   PW2      = 0xFE34;
sfr   PW3      = 0xFE36;
sfr   PWMIC    = 0xF17E;
sfr   PT0      = 0xF030;
sfr   PT1      = 0xF032;
sfr   PT2      = 0xF034;
sfr   PT3      = 0xF036;
sfr   PP0      = 0xF038;
sfr   PP1      = 0xF03A;
sfr   PP2      = 0xF03C;
sfr   PP3      = 0xF03E;
sbit  PTR0     = PWMCON0^0;
sbit  PTR1     = PWMCON0^1;
sbit  PTR2     = PWMCON0^2;
sbit  PTR3     = PWMCON0^3;
sbit  PTI0     = PWMCON0^4;
sbit  PTI1     = PWMCON0^5;
sbit  PTI2     = PWMCON0^6;
sbit  PTI3     = PWMCON0^7;
sbit  PIE0     = PWMCON0^8;
sbit  PIE1     = PWMCON0^9;
sbit  PIE2     = PWMCON0^10;
sbit  PIE3     = PWMCON0^11;
sbit  PIR0     = PWMCON0^12;
sbit  PIR1     = PWMCON0^13;
sbit  PIR2     = PWMCON0^14;
sbit  PIR3     = PWMCON0^15;
sbit  PEN0     = PWMCON1^0;
sbit  PEN1     = PWMCON1^1;
sbit  PEN2     = PWMCON1^2;
sbit  PEN3     = PWMCON1^3;
sbit  PM0      = PWMCON1^4;
sbit  PM1      = PWMCON1^5;
sbit  PM2      = PWMCON1^6;
sbit  PM3      = PWMCON1^7;
sbit  PB01     = PWMCON1^12;
sbit  PS2      = PWMCON1^14;
sbit  PS3      = PWMCON1^15;
sbit  PWMIR    = PWMIC^7;
sbit  PWMIE    = PWMIC^6;

/* SYSCON2 and SYSCON3 (only in some devices) */
sfr   SYSCON2  = 0xF1D0;
sbit  RCS      = SYSCON2^6;
sbit  SCS      = SYSCON2^7;
sbit  CLKLOCK  = SYSCON2^15;
sfr   SYSCON3  = 0xF1D4;
sbit  ADCDIS   = SYSCON3^0;
sbit  ASC0DIS  = SYSCON3^1;
sbit  SSCDIS   = SYSCON3^2;
sbit  GPT1DIS  = SYSCON3^3;
sbit  GPT2DIS  = SYSCON3^4;
sbit  FMDIS    = SYSCON3^5;
sbit  CC1DIS   = SYSCON3^6;
sbit  CC2DIS   = SYSCON3^7;
sbit  PWMDIS   = SYSCON3^9;
sbit  ASC1DIS  = SYSCON3^10;
sbit  I2CDIS   = SYSCON3^11;
sbit  CAN1DIS  = SYSCON3^13;
sbit  CAN2DIS  = SYSCON3^14;
sbit  PCDDIS   = SYSCON3^15;

/* X-Peripherals */
sfr   XP0IC    = 0xF186;
sfr   XP1IC    = 0xF18E;
sfr   XP2IC    = 0xF196;
sfr   XP3IC    = 0xF19E;
sbit  XP0IR    = XP0IC^7;
sbit  XP0IE    = XP0IC^6;
sbit  XP1IR    = XP1IC^7;
sbit  XP1IE    = XP1IC^6;
sbit  XP2IR    = XP2IC^7;
sbit  XP2IE    = XP2IC^6;
sbit  XP3IR    = XP3IC^7;
sbit  XP3IE    = XP3IC^6;

/* C167CS extensions */
sfr	XBCON1   = 0xF114;
sfr	XBCON2   = 0xF116;
sfr	XBCON5   = 0xF11C;
sfr	XADRS5   = 0xF01C;
#define RSTCON (*((unsigned int volatile sdata *) 0xF1E0))  // Reset Control Register

#endif