📄 21555.h
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/* 21555.h
*
*---------------------------------------------------------------------------
*
* I N T E L P R O P R I E T A R Y
*
* COPYRIGHT (c) 2000 BY INTEL CORPORATION. ALL RIGHTS
* RESERVED. NO PART OF THIS PROGRAM OR PUBLICATION MAY
* BE REPRODUCED, TRANSMITTED, TRANSCRIBED, STORED IN A
* RETRIEVAL SYSTEM, OR TRANSLATED INTO ANY LANGUAGE OR COMPUTER
* LANGUAGE IN ANY FORM OR BY ANY MEANS, ELECTRONIC, MECHANICAL,
* MAGNETIC, OPTICAL, CHEMICAL, MANUAL, OR OTHERWISE, WITHOUT
* THE PRIOR WRITTEN PERMISSION OF :
*
* INTEL CORPORATION
*
* 2200 MISSION COLLEGE BLVD
*
* SANTA CLARA, CALIFORNIA 95052-8119
*
*---------------------------------------------------------------------------
*
*
* system: IXP1200
* subsystem: EDU
* author: jjd, Apr 2, 01 Created
* --------------------------------------------------------------------------
*/
#ifndef __I21555_H__
#define __I21555_H__
#if defined(PRIMARY_SIDE)
#define PRIMARY_OFFSET 0x00
#define SECONDARY_OFFSET 0x40
#elif defined(SECONDARY_SIDE)
#define PRIMARY_OFFSET 0x40
#define SECONDARY_OFFSET 0x00
#else
#error PRIMARY_SIDE or SECONDARY_SIDE must be defined!
#endif
#define PCI_PRIMARY_DEVICE_ID (0x00+PRIMARY_OFFSET)
#define PCI_PRIMARY_VENDOR_ID (0x02+PRIMARY_OFFSET)
#define PCI_PRIMARY_COMMAND (0x04+PRIMARY_OFFSET)
#define PCI_PRIMARY_STATUS (0x06+PRIMARY_OFFSET)
#define PCI_PRIMARY_REVISION_ID (0x08+PRIMARY_OFFSET)
#define PCI_PRIMARY_CLASS_CODE (0x09+PRIMARY_OFFSET)
#define PCI_PRIMARY_CACHE_LINE_SZ (0x0c+PRIMARY_OFFSET)
#define PCI_PRIMARY_LATENCY (0x0d+PRIMARY_OFFSET)
#define PCI_PRIMARY_HEADER_TYPE (0x0e+PRIMARY_OFFSET)
#define PCI_PRIMARY_BIST (0x0f+PRIMARY_OFFSET)
#define PCI_PRIMARY_INT_LINE (0x3c+PRIMARY_OFFSET)
#define PCI_PRIMARY_INT_PIN (0x3d+PRIMARY_OFFSET)
#define PCI_PRIMARY_MIN_GRANT (0x3e+PRIMARY_OFFSET)
#define PCI_PRIMARY_MAX_LATENCY (0x3f+PRIMARY_OFFSET)
#define PCI_SECONDARY_DEVICE_ID (0x00+SECONDARY_OFFSET)
#define PCI_SECONDARY_VENDOR_ID (0x02+SECONDARY_OFFSET)
#define PCI_SECONDARY_COMMAND (0x04+SECONDARY_OFFSET)
#define PCI_SECONDARY_STATUS (0x06+SECONDARY_OFFSET)
#define PCI_SECONDARY_REVISION_ID (0x08+SECONDARY_OFFSET)
#define PCI_SECONDARY_CLASS_CODE (0x09+SECONDARY_OFFSET)
#define PCI_SECONDARY_CACHE_LINE_SZ (0x0c+SECONDARY_OFFSET)
#define PCI_SECONDARY_LATENCY (0x0d+SECONDARY_OFFSET)
#define PCI_SECONDARY_HEADER_TYPE (0x0e+SECONDARY_OFFSET)
#define PCI_SECONDARY_BIST (0x0f+SECONDARY_OFFSET)
#define PCI_SECONDARY_INT_LINE (0x3c+SECONDARY_OFFSET)
#define PCI_SECONDARY_INT_PIN (0x3d+SECONDARY_OFFSET)
#define PCI_SECONDARY_MIN_GRANT (0x3e+SECONDARY_OFFSET)
#define PCI_SECONDARY_MAX_LATENCY (0x3f+SECONDARY_OFFSET)
#define PCI_PRIMARY_CSR_DS_MEM0_BAR (0x10+PRIMARY_OFFSET)
#define PCI_PRIMARY_CSR_IO_BAR (0x14+PRIMARY_OFFSET)
#define PCI_PRIMARY_DS_IO_MEM1_BAR (0x18+PRIMARY_OFFSET)
#define PCI_PRIMARY_DS_MEM2_BAR (0x1c+PRIMARY_OFFSET)
#define PCI_PRIMARY_DS_MEM3_BAR (0x20+PRIMARY_OFFSET)
#define PCI_PRIMARY_UPPER32_MEM3_BAR (0x24+PRIMARY_OFFSET)
#define PCI_SECONDARY_CSR_MEM_BAR (0x10+SECONDARY_OFFSET)
#define PCI_SECONDARY_CSR_IO_BAR (0x14+SECONDARY_OFFSET)
#define PCI_SECONDARY_US_IO_MEM1_BAR (0x18+SECONDARY_OFFSET)
#define PCI_SECONDARY_US_MEM1_BAR (0x1c+SECONDARY_OFFSET)
#define PCI_SECONDARY_US_MEM2_BAR (0x20+SECONDARY_OFFSET)
#define PCI_CHIP_CTRL0 (0xcc)
#define PCI_CHIP_CTRL0_MasterAbtMode (1<<0)
#define PCI_CHIP_CTRL0_MemWriteDisconnect (1<<1)
#define PCI_CHIP_CTRL0_PriMasterTO (1<<2)
#define PCI_CHIP_CTRL0_SecMasterTO (1<<3)
#define PCI_CHIP_CTRL0_PriMasterTODisable (1<<4)
#define PCI_CHIP_CTRL0_SecMasterTODisable (1<<5)
#define PCI_CHIP_CTRL0_DelayXactionOrderCtrl (1<<6)
#define PCI_CHIP_CTRL0_SerrFwdEnable (1<<7)
#define PCI_CHIP_CTRL0_UsDACPrefetchDisable (1<<8)
#define PCI_CHIP_CTRL0_MultiDevEnable (1<<9)
#define PCI_CHIP_CTRL0_PriAccessLockout (1<<10)
#define PCI_CHIP_CTRL0_SecClkDisable (1<<11)
#define PCI_CHIP_CTRL0_LUTPgSzExt (1<<12)
#define PCI_CHIP_CTRL0_RetryCntr (1<<13)
#define PCI_CHIP_CTRL0_VGAModeMask (3<<14)
#define PCI_CHIP_CTRL0_VGAModeIgnored (0<<14)
#define PCI_CHIP_CTRL0_VGAModePriForward (1<<14)
#define PCI_CHIP_CTRL0_VGAModeSecForward (2<<14)
#define PCI_CHIP_CTRL1 (0xce)
#define PCI_CHIP_STATUS (0xd0)
#define PCI_CHIP_STATUS_DsDelayMasterTO (1<<0)
#define PCI_CHIP_STATUS_DsDelayReadDiscard (1<<1)
#define PCI_CHIP_STATUS_DsDelayWriteDiscard (1<<2)
#define PCI_CHIP_STATUS_DsPostWriteDataDiscard (1<<3)
#define PCI_CHIP_STATUS_UsDelayMasterTO (1<<8)
#define PCI_CHIP_STATUS_UsDelayReadDiscard (1<<9)
#define PCI_CHIP_STATUS_UsDelayWriteDiscard (1<<10)
#define PCI_CHIP_STATUS_UsPostWriteDataDiscard (1<<11)
#define PCI_DS_IO_MEM1_XLAT_BASE (0x98)
#define PCI_US_IO_MEM0_XLAT_BASE (0xa4)
#define PCI_DS_MEM0_XLAT_BASE (0x94)
#define PCI_DS_MEM2_XLAT_BASE (0x9c)
#define PCI_DS_MEM3_XLAT_BASE (0xa0)
#define PCI_US_MEM1_XLAT_BASE (0xa8)
#define PCI_DS_IO_MEM1_SETUP (0xb0)
#define PCI_US_IO_MEM0_SETUP (0xc4)
#define PCI_DS_MEM0_SETUP (0xac)
#define PCI_DS_MEM2_SETUP (0xb4)
#define PCI_DS_MEM3_SETUP (0xb8)
#define PCI_US_MEM1_SETUP (0xc8)
#define PCI_UPPER32_DS_MEM3_SETUP (0xbc)
#define PCI_DS_CFG_ADDR (0x80)
#define PCI_US_CFG_ADDR (0x88)
#define PCI_DS_CFG_DATA (0x84)
#define PCI_uS_CFG_DATA (0x8c)
#define PCI_CFG_DS_OWN (0x90)
#define PCI_CFG_US_OWN (0x91)
#define PCI_CFG_CSR (0x92)
/* parallel rom section */
#define PCI_PRIMARY_XROM_BAR (0x30+PRIMARY_OFFSET)
#define PCI_PRIMARY_XROM_BAR_DecodeEnable (1<<0)
#define PCI_PRIMARY_XROM_SETUP (0xc0)
#define PCI_PRIMARY_XROM_SETUP_Enable (1<<24)
/* serial rom section */
#define PCI_SROM_MODE (0xd6)
#define PCI_SROM_MODE_Preload (1<<0)
#define PCI_SROM_MODE_PriLockoutReset (1<<1)
#define PCI_SROM_MODE_SyncEnable (1<<2)
#define PCI_SROM_MODE_SclkEnable (1<<3)
#define PCI_SROM_MODE_SecCFNEnable (1<<4)
#define PCI_SROM_MODE_ArbiterEnable (1<<5)
#define PCI_SROM_MODE_Pri64Extension (1<<6)
#define PCI_SROM_MODE_Sec64Extension (1<<7)
/* error handling section */
#define PCI_PRIMARY_SERR_DISABLE (0xd4)
#define PCI_SECONDARY_SERR_DISABLE (0xd5)
/* more io mapped CSRs */
#define I21555_DS_CFG_ADDR 0x00
#define I21555_DS_CFG_DATA 0x04
#define I21555_US_CFG_ADDR 0x08
#define I21555_US_CFG_DATA 0x0c
#define I21555_DS_CFG_OWN 0x10
#define I21555_US_CFG_OWN 0x11
#define I21555_CFG_CSR 0x12
#define I21555_DS_IO_ADDR 0x14
#define I21555_DS_IO_DATA 0x18
#define I21555_US_IO_ADDR 0x1c
#define I21555_US_IO_DATA 0x20
#define I21555_DS_IO_OWN 0x24
#define I21555_US_IO_OWN 0x25
#define I21555_IO_OWN_CSR 0x26
#define I21555_LUT_OFFSET 0x28
#define I21555_LUT_DATA 0x2c
#define I21555_I2O_OUT_POST_STATUS 0x30
#define I21555_I2O_OUT_POST_MASK 0x34
#define I21555_I2O_IN_POST_STATUS 0x38
#define I21555_I2O_IN_POST_MASK 0x3c
#define I21555_I2O_IN_QUEUE 0x40
#define I21555_I2O_OUT_QUEUE 0x44
#define I21555_I2O_IN_FREE_HEAD 0x48
#define I21555_I2O_IN_POST_TAIL 0x4c
#define I21555_I2O_OUT_FREE_TAIL 0x50
#define I21555_I2O_OUT_POST_HEAD 0x54
#define I21555_I2O_IN_POST_COUNTER 0x58
#define I21555_I2O_IN_FREE_COUNTER 0x5c
#define I21555_I2O_OUT_POST_COUNTER 0x60
#define I21555_I2O_OUT_FREE_COUNTER 0x64
#define I21555_DS_MEM0_XLAT_BASE 0x68
#define I21555_DS_IO_MEM1_XLAT_BASE 0x6c
#define I21555_DS_MEM2_XLAT_BASE 0x70
#define I21555_DS_MEM3_XLAT_BASE 0x74
#define I21555_US_IO_MEM0_XLAT_BASE 0x78
#define I21555_US_MEM1_XLAT_BASE 0x7c
#define I21555_CHIP_CTRL 0x80
/* interrupt and scratchpad section, memory or io space */
#define I21555_CHIP_STATUS (0x82)
#define I21555_CHIP_STATUS_PowerMgmt (1<<0)
#define I21555_CHIP_STATUS_SubsytemEvent (1<<1)
#define I21555_CHIP_SET_IRQ_MASK (0x84)
#define I21555_CHIP_SET_IRQ_MASK_PowerMgmt (1<<0)
#define I21555_CHIP_SET_IRQ_MASK_SubsystemEvent (1<<1)
#define I21555_CHIP_CLEAR_IRQ_MASK (0x86)
#define I21555_CHIP_CLEAR_IRQ_MASK_PowerMgmt (1<<0)
#define I21555_CHIP_CLEAR_IRQ_MASK_SubsystemEvent (1<<1)
#define I21555_US_PAGE_BD_IRQ0 (0x88)
#define I21555_US_PAGE_BD_IRQ1 (0x8c)
#define I21555_US_PAGE_BD_IRQ0_MASK (0x90)
#define I21555_US_PAGE_BD_IRQ1_MASK (0x94)
#define I21555_PRIMARY_CLEAR_IRQ (0x98)
#define I21555_SECONDARY_CLEAR_IRQ (0x9a)
#define I21555_PRIMARY_SET_IRQ (0x9c)
#define I21555_SECONDARY_SET_IRQ (0x9e)
#define I21555_PRIMARY_CLEAR_IRQ_MASK (0xa0)
#define I21555_SECONDARY_CLEAR_IRQ_MASK (0xa2)
#define I21555_PRIMARY_SET_IRQ_MASK (0xa4)
#define I21555_SECONDARY_SET_IRQ_MASK (0xa6)
#define I21555_SCRATCH0 (0xa8)
#define I21555_SCRATCH1 (0xac)
#define I21555_SCRATCH2 (0xb0)
#define I21555_SCRATCH3 (0xb4)
#define I21555_SCRATCH4 (0xb8)
#define I21555_SCRATCH5 (0xbc)
#define I21555_SCRATCH6 (0xc0)
#define I21555_SCRATCH7 (0xc4)
/* these are through memory or io */
#define I21555_ROM_SETUP (0xc8)
#define I21555_ROM_DATA (0xca)
#define I21555_ROM_ADDR (0xcc)
#define I21555_ROM_ADDR_OpGeneral (0<<9)
#define I21555_ROM_ADDR_WriteEnable ((3<<7)|I21555_ROM_ADDR_OpGeneral)
#define I21555_ROM_ADDR_EraseAll ((2<<7)|I21555_ROM_ADDR_OpGeneral)
#define I21555_ROM_ADDR_WriteAll ((1<<7)|I21555_ROM_ADDR_OpGeneral)
#define I21555_ROM_ADDR_WriteDisable (0<<7)
#define I21555_ROM_ADDR_Write (1<<9)
#define I21555_ROM_ADDR_Read (2<<9)
#define I21555_ROM_ADDR_Erase (3<<9)
#define I21555_ROM_CTRL (0xcf)
#define I21555_ROM_CTRL_SromStartBusy (1<<0)
#define I21555_ROM_CTRL_PromStartBusy (1<<1)
#define I21555_ROM_CTRL_Write (1<<2)
#define I21555_ROM_CTRL_Read (0<<2)
#define I21555_ROM_CTRL_SromPoll (1<<3)
#define I21555_GENERIC_OWN (0xd0)
#define I21555_GENERIC_OWN_Own0 (1<<0)
#define I21555_GENERIC_OWN_Own1 (1<<8)
#define I21555_GENERIC_OWN_Own0Status (1<<16)
#define I21555_GENERIC_OWN_Own1Status (1<<17)
#define I21555_US_MEM2_LUT 0x100
#define SROM_NUM_BYTES 0x43
/* externs */
#ifndef _ASMLANGUAGE
typedef unsigned long UINT32;
typedef unsigned short UINT16;
typedef unsigned char UINT8;
int i21555Init (void);
int i21555SromReprogramAll (UINT8 *newData);
int i21555SromDump (UINT8 *data);
int i21555SromEraseAll(void);
#endif /* _ASMLANGUAGE */
#endif /* __I21555_H__ */
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