📄 21555drv.c
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/* 21555drv.c - Intel 21555 Non-Transparent Bridge Driver */
/* Copyright 2000 Intel Corp. */
/*
modification history
--------------------
01a,20dec00,jdg Created
*/
/*
DESCRIPTION
This library provides support for the Intel 21555 Non-transparent Bridge.
*/
/* includes */
#include "vxWorks.h"
#include "config.h"
#include "dllLib.h"
#include "pciIomapLib.h"
#include "21555drv.h"
/* defines */
#define MASK_4K (~(4 * 1024 - 1))
#define MASK_8K (~(8 * 1024 - 1))
#define MASK_1M (~(1 * 1024 * 1024 -1))
#define MASK_2M (~(2 * 1024 * 1024 -1))
/*
* At present, we only use bit 15, later we'll also use bit 14 for the
* second 1200
*/
#define DOORBELL_BITS (1 << 15)
#define REG_READ16(a) (*(volatile UINT16*)(a))
#define REG_WRITE16(a,val) (*(volatile UINT16*)(a)) = (val)
/* imports */
/* typedefs */
typedef struct ntbInfo /* Non transparent bridge info */
{
UINT32 ioBase;
} NTB_INFO;
/* globals */
NTB_INFO ntbInfo;
/* locals */
/* forward declarations */
/*******************************************************************************
*
* sysIntel21555Init - Initialize 21555 NTB
*
* This routine finds the bridge and initializes it's CSRs
*
* RETURNS: OK, or ERROR
*/
STATUS sysIntel21555Init (short vendId, short sysId)
{
UINT32 pciBus; /* PCI bus number */
UINT32 pciDevice; /* PCI device number */
UINT32 pciFunc; /* PCI Function number */
UINT32 addr;
UINT16 data;
if (OK != pciFindDevice(INT21555_VEND_ID, INT21555_DEVICE_ID,
0, &pciBus, &pciDevice, &pciFunc))
{
return ERROR;
}
/* Read CSR IO Base */
pciConfigInLong(pciBus, pciDevice, pciFunc, PCI_CFG_BASE_ADDRESS_1,
&ntbInfo.ioBase); /* CSR IO Base */
ntbInfo.ioBase &= ~PCI_HEADER_TYPE_MASK;
ntbInfo.ioBase |= PCI_IO_BASE;
/* Set Subsystem ID */
pciConfigOutWord(pciBus, pciDevice, pciFunc, PCI_CFG_SUB_VENDER_ID,
vendId);
pciConfigOutWord(pciBus, pciDevice, pciFunc, PCI_CFG_SUB_SYSTEM_ID,
sysId);
/*
* Set up primary BAR masks and address mapping
*
* ADDR REG TYPE SIZE PURPOSE
* 10 Pri CSR / DS Mem 0 Mem N/A
* 14 Pri CSR IO 256 21555 CSRs
* 18 Downstream IOM Bar 1 Mem 1(2)M MEM/CSR 0/1 (1200's CSRs)
* 1C Downstream Mem Bar 2 Mem 4K MEM 0 (1200's SDRAM)
* 20 Downstream Mem Bar 3 Mem 4K MEM 1 (unused at present)
*/
pciConfigOutLong(pciBus, pciDevice, pciFunc,
PCI_DS_IOMEM_1_SETUP, MASK_1M);
pciConfigOutLong(pciBus, pciDevice, pciFunc,
PCI_DS_MEM_2_SETUP, MASK_4K);
/* IOMEM_1 is set to point to our CSR MEM base */
addr = *(UINT32 *) (IXP1200_PCI_MEM_BAR);
pciConfigOutLong(pciBus, pciDevice, pciFunc,
PCI_DS_IOMEM_1_TBASE, addr);
/* MEM_2 is set to point to 4K before the start of VxWorks memory */
addr = *(UINT32 *) (IXP1200_PCI_DRAM_BAR); /* addr of SDRAM */
addr += RESERVED_LOW_MEM - (4 * 1024);
pciConfigOutLong(pciBus, pciDevice, pciFunc,
PCI_DS_MEM_2_TBASE, addr);
/* Set secondary PCI command reg to allow transactions */
pciConfigOutWord(pciBus, pciDevice, pciFunc,
PCI_CFG_COMMAND,
PCI_CMD_IO_ENABLE |
PCI_CMD_MEM_ENABLE |
PCI_CMD_MASTER_ENABLE);
/* Allow primary PCI to do config cycles */
pciConfigInWord(pciBus, pciDevice, pciFunc,
PCI_CHIP_CTRL_0,
&data);
data &= ~(PCI_CHIP_C0_PR_ACC_LOCK);
pciConfigOutWord(pciBus, pciDevice, pciFunc,
PCI_CHIP_CTRL_0,
data);
/* Program Doorbell register */
/* Clear interrupt request */
REG_WRITE16(ntbInfo.ioBase + PCI_PRI_CLR_IRQ, DOORBELL_BITS);
/* Enable doorbell */
REG_WRITE16(ntbInfo.ioBase + PCI_PRI_CLR_IRQ_MASK, DOORBELL_BITS);
return OK;
}
/*******************************************************************************
*
* sysGet21555DBAddr - Get 21555 doorbell set address
*
* This routine returns the address of the 21555 doorbell set register
*
* RETURNS: Address
*/
UINT32 sysGet21555DBAddr ()
{
return (ntbInfo.ioBase + PCI_PRI_SET_IRQ);
}
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