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; Clock frequency for UART
IF :DEF: SA1200_A0
UART_CLOCK EQU 100000000/32
ELSE
UART_CLOCK EQU 3686400
ENDIF
BAUD_9600 EQU ((UART_CLOCK/16/9600)-1) << 16
BAUD_19200 EQU ((UART_CLOCK/16/19200)-1) << 16
BAUD_38400 EQU ((UART_CLOCK/16/38400)-1) << 16
BAUD_57600 EQU ((UART_CLOCK/16/57600)-1) << 16
BAUD_115200 EQU ((UART_CLOCK/16/115200)-1) << 16
;UART_CR_VALUE EQU (BAUD_9600 + UART_ENABLE_BIT + UART_DATA_BITS_8)
;UART_CR_VALUE EQU 0x1300E0
CLEAR_BAUD_RATE_FIELD EQU (0x3FF << 16)
; UART Data Register with Error Status
UART_DATA_FRMING_ERR EQU BIT10
UART_DATA_RX_OVERRUN EQU BIT9
UART_DATA_PARITY_ERR EQU BIT8
; ----------------
; PCI Control Unit
; ----------------
CSR_BASE EQU 0x42000000
PCI_VENDOR_ID EQU 0x00
PCI_DEVICE_ID EQU 0x02
PCI_COMMAND EQU 0x04
PCI_STATUS EQU 0x06
PCI_REV_ID EQU 0x08
PCI_CLASS_ID EQU 0x09
PCI_LATENCY EQU 0x0D
PCI_MEM_BAR EQU 0x10
PCI_CSR_BAR EQU 0x10
PCI_IO_BAR EQU 0x14
PCI_DRAM_BAR EQU 0x18
PCI_OUT_INT_STATUS EQU 0x30
PCI_OUT_INT_MASK EQU 0x34
PCI_INT_LINE EQU 0x3C
MAILBOX_0 EQU 0x50
MAILBOX_1 EQU 0x54
MAILBOX_2 EQU 0x58
MAILBOX_3 EQU 0x5C
DOORBELL EQU 0x60
DOORBELL_SETUP EQU 0x64
ROM_BYTE_WRITE EQU 0x68
CAP_PTR_EXT EQU 0x70
PWR_MGMT EQU 0x74
PCI_RESET EQU 0x7C
CHAN_1_BYTE_COUNT EQU 0x80
CHAN_1_PCI_ADDR EQU 0x84
CHAN_1_DRAM_ADDR EQU 0x88
CHAN_1_DESC_PTR EQU 0x8C
CHAN_1_CONTROL EQU 0x90
DMA_INF_MODE EQU 0x9C
CHAN_2_BYTE_COUNT EQU 0xA0
CHAN_2_PCI_ADDR EQU 0xA4
CHAN_2_DRAM_ADDR EQU 0xA8
CHAN_2_DESC_PTR EQU 0xAC
CHAN_2_CONTROL EQU 0xB0
CSR_BASE_ADDR_MASK EQU 0xF8
;CSR_BASE_ADDR_OFF EQU 0xFC
DRAM_BASE_ADDR_MASK EQU 0x100
;DRAM_BASE_ADDR_OFF EQU 0x104
;ROM_BASE_ADDR_MASK EQU 0x108
;DRAM_TIMING EQU 0x10C
;DRAM_ADDR_SIZE_0 EQU 0x110
;DRAM_ADDR_SIZE_1 EQU 0x114
;DRAM_ADDR_SIZE_2 EQU 0x118
;DRAM_ADDR_SIZE_3 EQU 0x11C
I2O_IFH EQU 0x120
I2O_IPT EQU 0x124
I2O_OPH EQU 0x128
I2O_OFT EQU 0x12C
I2O_IFC EQU 0x130
I2O_OPC EQU 0x134
I2O_IPC EQU 0x138
SA_CONTROL EQU 0x13C
PCI_ADDR_EXT EQU 0x140
PREFETCH_RANGE EQU 0x144
PCI_ABITOR_STATUS EQU 0x148
DBELL_PCI_MASK EQU 0x150
DBELL_SA_MASK EQU 0x154
IRQ_STATUS EQU 0x180
IRQ_RAW_STATUS EQU 0x184
IRQ_ENABLE EQU 0x188
IRQ_ENABLE_SET EQU 0x188
IRQ_ENABLE_CLEAR EQU 0x18C
IRQ_SOFT EQU 0x190
FIQ_STATUS EQU 0x280
FIQ_RAW_STATUS EQU 0x284
FIQ_ENABLE EQU 0x288
FIQ_ENABLE_SET EQU 0x288
FIQ_ENABLE_CLEAR EQU 0x28C
FIQ_SOFT EQU 0x290
TIMER_1_LOAD EQU 0x300
TIMER_1_VALUE EQU 0x304
TIMER_1_CONTROL EQU 0x308
TIMER_1_CLEAR EQU 0x30C
TIMER_2_LOAD EQU 0x320
TIMER_2_VALUE EQU 0x324
TIMER_2_CONTROL EQU 0x328
TIMER_2_CLEAR EQU 0x32C
TIMER_3_LOAD EQU 0x340
TIMER_3_VALUE EQU 0x344
TIMER_3_CONTROL EQU 0x348
TIMER_3_CLEAR EQU 0x34C
TIMER_4_LOAD EQU 0x360
TIMER_4_VALUE EQU 0x364
TIMER_4_CONTROL EQU 0x368
TIMER_4_CLEAR EQU 0x36C
; ----------------------------
; PCI_RESET Register Constants
; ----------------------------
UENG0_RST EQU BIT0
UENG1_RST EQU BIT1
UENG2_RST EQU BIT2
UENG3_RST EQU BIT3
UENG4_RST EQU BIT4
UENG5_RST EQU BIT5
PCIRST_RST EQU BIT14
EXT_RST EQU BIT15
FBI_RST EQU BIT16
FXCMD_RST EQU BIT17
SDRAM_RST EQU BIT18
SRAM_RST EQU BIT29
PCI_RST EQU BIT30
SACORE_RST EQU BIT31
; ------------------------------
; ARM control register constants
; ------------------------------
INIT_COMPLETE EQU BIT0
PCI_NRESET EQU BIT9
PCI_CFN EQU BIT31
ROM_TIMING EQU 0x0fff0000
ROM_SETUP EQU 0x04aa0000
SA_CTL_COMPLETE EQU (INIT_COMPLETE | PCI_NRESET)
; ---------------
; Interrupt Flags
; ---------------
SOFT_INT EQU BIT1
TIMER1_INT EQU BIT4
TIMER2_INT EQU BIT5
TIMER3_INT EQU BIT6
TIMER4_INT EQU BIT7
DOORBELL_INT EQU BIT15
DMA1_INT EQU BIT16
DMA2_INT EQU BIT17
PCI_IRQ_L_INT EQU BIT18
DMA1_NOT_BUSY_INT EQU BIT20
DMA2_NOT_BUSY_INT EQU BIT21
START_BIST_INT EQU BIT22
SERR_INT EQU BIT23
SDRAM_PARITY_INT EQU BIT24
I2O_INPOST_INT EQU BIT25
DISCARD_TIMER_INT EQU BIT27
DATA_PARITY_INT EQU BIT28
PCI_MASTER_ABORT_INT EQU BIT29
PCI_TARGET_ABORT_INT EQU BIT30
PCI_PARITY_INT EQU BIT31
; -------------------------------
; Timer Control Register Constant
; -------------------------------
TIMER_ENABLE EQU BIT7
TIMER_MODE EQU BIT6
OS_TIMER EQU 3
; these timers below now (since B0 port) should be made into variables
; B0/A board backward compatability does not depend on a
; definition of a constant (like SA1200_A0)
; IF :DEF: SA1200_A0
;mSEC_1 EQU (100000000 / 1000)
; ELSE
;mSEC_1 EQU (162200000 / 1000) ; A board
;mSEC_1 EQU (165890000 / 1000) ; B0 value
; ENDIF
;mSEC_5 EQU (mSEC_1 * 5)
;mSEC_10 EQU (mSEC_1 * 10)
;mSEC_100 EQU (mSEC_1 * 100)
;SEC_1 EQU (mSEC_1 * 1000)
;
; --------------
; SRAM Registers
; --------------
SRAM_CSR EQU 0x38000000
SRAM_SLOW_CONFIG EQU 0x38000020
SRAM_BOOT_CONFIG EQU 0x38000024
SRAM_SLOWPORT_CONFIG EQU 0x38000028
; ------------------
; SRAM CSR constants
; ------------------
SRAM_CFT EQU BIT18
SRAM_MAC EQU BIT17
SRAM_FLWT EQU BIT16
SRAM_BKW EQU BIT15
SRAM_8MF EQU BIT14
SRAM_4MF EQU BIT13
SRAM_2MF EQU BIT12
SRAM_8MSR EQU BIT11
SRAM_4MSR EQU BIT10
SRAM_2MSR EQU BIT9
SRAM_1MSR EQU BIT8
SRAM_RLAM EQU BIT4
SRAM_IRQ EQU BIT3
SRAM_FIQ EQU BIT2
SRAM_RLRS EQU BIT1
SRAM_RLS EQU BIT0
IF :DEF: SA1200_A0
SRAM_CSR_VALUE EQU (SRAM_8MF + SRAM_8MSR)
SRAM_SLOW_CONFIG_VALUE EQU 0x00000B0D
SRAM_BOOT_CONFIG_VALUE EQU 0x090A0501
SRAM_SLOWPORT_CONFIG_V EQU 0x0B0C0703
ELSE
SRAM_CSR_VALUE EQU (SRAM_8MF + SRAM_8MSR)
SRAM_SLOW_CONFIG_VALUE EQU 0x0000184A
SRAM_SLOW_CONFIG_V_165 EQU 0x00001852
SRAM_BOOT_CONFIG_VALUE EQU 0x18180400
SRAM_SLOWPORT_CONFIG_V EQU 0x3E440C06
SRAM_SLOPORT_CFG_V_165 EQU 0x454B0E07
ENDIF
; ---------------
; SDRAM Registers
; ---------------
SDRAM_CSR EQU 0xFF000000
SDRAM_MEMCTL0 EQU 0xFF000004
SDRAM_MEMCTL1 EQU 0xFF000008
SDRAM_MEMINIT EQU 0xFF00000C
; -------------------
; SDRAM CSR Constants
; -------------------
SDRAM_EN_FTST EQU BIT15
SDRAM_EN_INT EQU BIT10
SDRAM_EN_IRQ EQU BIT9
SDRAM_EN_FIQ EQU BIT8
SDRAM_EN_CPE EQU BIT6
SDRAM_EN_PCIPE EQU BIT5
SDRAM_EN_UEPE EQU BIT4
SDRAM_GENPAR EQU BIT3
SDRAM_EVENPAR EQU BIT2
SDRAM_TF_BENDN EQU BIT1
SDRAM_INIT EQU BIT0
IF :DEF: SA1200_A0
SDRAM_CSR_VALUE EQU (SDRAM_INIT + SDRAM_EVENPAR)
SDRAM_MEMCTL0_VALUE EQU 0x050082B9
SDRAM_MEMCTL1_VALUE EQU 0x21282252
SDRAM_MEMINIT_VALUE EQU 0x00000000
ELSE
SDRAM_CSR_VALUE EQU 0x00000001
SDRAM_MEMCTL0_VALUE_165 EQU 0x04F482C8
SDRAM_MEMCTL1_VALUE_165 EQU 0x12262252
SDRAM_MEMINIT_VALUE_165 EQU 0x00EF1FAF
SDRAM_MEMCTL0_VALUE EQU 0x061A82C8
SDRAM_MEMCTL1_VALUE EQU 0x12361141
SDRAM_MEMINIT_VALUE EQU 0x00122710
ENDIF
;define fast clock and B0 params
CCCR_INIT_VALUE_A EQU (PLL_A_CLK_162MHz)
CCCR_INIT_VALUE EQU (PLL_CLK_200MHz)
ENDIF ; __address_h
END ; end of file
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