📄 platform.s
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; platform.s
;
;------------------------------------------------------------
;
; I N T E L P R O P R I E T A R Y
;
; COPYRIGHT (c) 1999 BY INTEL CORPORATION. ALL RIGHTS
; RESERVED. NO PART OF THIS PROGRAM OR PUBLICATION MAY
; BE REPRODUCED, TRANSMITTED, TRANSCRIBED, STORED IN A
; RETRIEVAL SYSTEM, OR TRANSLATED INTO ANY LANGUAGE OR COMPUTER
; LANGUAGE IN ANY FORM OR BY ANY MEANS, ELECTRONIC, MECHANICAL,
; MAGNETIC, OPTICAL, CHEMICAL, MANUAL, OR OTHERWISE, WITHOUT
; THE PRIOR WRITTEN PERMISSION OF :
;
; INTEL CORPORATION
;
; 2200 MISSION COLLEGE BLVD
;
; SANTA CLARA, CALIFORNIA 95052-8119
;
;------------------------------------------------------------
; system: SA1200
; subsystem: UCOS
; author: Henry Qian 01/29/99
; revisions:
;
; 03/31/00 - Dan White - added Rev B0 changes to startup
; 04/25/00 - Dan White - added 200MHz changes
;
IF :LNOT: :DEF: __address_h
__address_h EQU 1
BIT0 EQU 0x00000001
BIT1 EQU 0x00000002
BIT2 EQU 0x00000004
BIT3 EQU 0x00000008
BIT4 EQU 0x00000010
BIT5 EQU 0x00000020
BIT6 EQU 0x00000040
BIT7 EQU 0x00000080
BIT8 EQU 0x00000100
BIT9 EQU 0x00000200
BIT10 EQU 0x00000400
BIT11 EQU 0x00000800
BIT12 EQU 0x00001000
BIT13 EQU 0x00002000
BIT14 EQU 0x00004000
BIT15 EQU 0x00008000
BIT16 EQU 0x00010000
BIT17 EQU 0x00020000
BIT18 EQU 0x00040000
BIT19 EQU 0x00080000
BIT20 EQU 0x00100000
BIT21 EQU 0x00200000
BIT22 EQU 0x00400000
BIT23 EQU 0x00800000
BIT24 EQU 0x01000000
BIT25 EQU 0x02000000
BIT26 EQU 0x04000000
BIT27 EQU 0x08000000
BIT28 EQU 0x10000000
BIT29 EQU 0x20000000
BIT30 EQU 0x40000000
BIT31 EQU 0x80000000
ALL_BITS EQU 0xFFFFFFFF
SZ_1K EQU 0x00000400
SZ_4K EQU 0x00001000
SZ_8K EQU 0x00002000
SZ_16K EQU 0x00004000
SZ_32K EQU 0x00008000
SZ_64K EQU 0x00010000
SZ_128K EQU 0x00020000
SZ_256K EQU 0x00040000
SZ_512K EQU 0x00080000
SZ_1M EQU 0x00100000
SZ_2M EQU 0x00200000
SZ_4M EQU 0x00400000
SZ_8M EQU 0x00800000
SZ_16M EQU 0x01000000
SZ_32M EQU 0x02000000
SZ_64M EQU 0x04000000
SZ_128M EQU 0x08000000
SZ_256M EQU 0x10000000
SZ_512M EQU 0x20000000
SZ_1G EQU 0x40000000
; --------------------------------
; SA1200 physical memory addresses
; --------------------------------
ROMBase EQU 0x00000000
ROMSize EQU SZ_1M
SRAMBase EQU 0x10000000
SRAMSize EQU (SZ_512M + SZ_256M)
PCILocalBase EQU 0x42000000
PCILocalSize EQU SZ_1M
PCIConfigTypeOneBase EQU 0x52000000
PCIConfigTypeOneSize EQU SZ_32M
PCIConfigTypeZeroBase EQU 0x53000000
PCIConfigTypeZeroSize EQU SZ_32M
PCIIOBase EQU 0x54000000
PCIIOSize EQU SZ_1M
PCIMemBase EQU 0x60000000
PCIMemSize EQU SZ_512M
ARMCOREBase EQU 0x90000000
ARMCORESize EQU SZ_1M
AMBABase EQU 0xB0000000
AMBASize EQU SZ_1M
DRAMBase EQU 0xC0000000
DRAMSize EQU SZ_8M
DRAMPrefetchBase EQU 0xD0000000
DRAMPrefetchSize EQU DRAMSize
DRAMFlushBase EQU 0xE0000000
DRAMFlushSize EQU DRAMSize
DRAMControlBase EQU 0xFF000000
DRAMControlSize EQU SZ_1M
; ----------------------------
; MMU Virtual SA1200 Addresses
; ----------------------------
DRAM_BASE EQU 0x00000000
DRAM_SIZE EQU DRAMSize
ROM_BASE EQU 0x08000000
ROM_SIZE EQU ROMSize
SRAM_BASE EQU SRAMBase
SRAM_SIZE EQU SZ_8M
; ================
; SA1200 REGISTERS
; ================
; --------------------------
; PLL Configuration Register
; --------------------------
PLL_CFG EQU 0x90000C00
; PLL_CFG Constants @ 3.6864 MHz
;
PLL_A_CLK_29MHz EQU 0x00
PLL_A_CLK_36MHz EQU 0x01
PLL_A_CLK_44MHz EQU 0x02
PLL_A_CLK_51MHz EQU 0x03
PLL_A_CLK_58MHz EQU 0x04
PLL_A_CLK_66MHz EQU 0x05
PLL_A_CLK_73MHz EQU 0x06
PLL_A_CLK_81MHz EQU 0x07
PLL_A_CLK_88MHz EQU 0x08
PLL_A_CLK_95MHz EQU 0x09
PLL_A_CLK_103MHz EQU 0x0A
PLL_A_CLK_110MHz EQU 0x0B
PLL_A_CLK_117MHz EQU 0x0C
PLL_A_CLK_132MHz EQU 0x0D
PLL_A_CLK_147MHz EQU 0x0E
PLL_A_CLK_154MHz EQU 0x0F
PLL_A_CLK_162MHz EQU 0x10
PLL_A_CLK_176MHz EQU 0x11
PLL_A_CLK_191MHz EQU 0x12
PLL_CLK_29MHz EQU 0x00
PLL_CLK_36MHz EQU 0x01
PLL_CLK_44MHz EQU 0x02
PLL_CLK_51MHz EQU 0x03
PLL_CLK_58MHz EQU 0x04
PLL_CLK_66MHz EQU 0x05
PLL_CLK_73MHz EQU 0x06
PLL_CLK_81MHz EQU 0x07
PLL_CLK_88MHz EQU 0x08
PLL_CLK_95MHz EQU 0x09
PLL_CLK_103MHz EQU 0x0A
PLL_CLK_110MHz EQU 0x0B
PLL_CLK_132MHz EQU 0x0C
PLL_CLK_147MHz EQU 0x0D
PLL_CLK_154MHz EQU 0x0E
PLL_CLK_162MHz EQU 0x0F
PLL_CLK_165MHz EQU 0x10
PLL_CLK_176MHz EQU 0x11
; ------------------------------
; FBI Control & Status Registers
; ------------------------------
IREG EQU 0xB00401E0
; IREG Contants
UEFIQ_ENABLE EQU BIT31
UEIRQ_ENABLE EQU BIT30
CINTFIQ_ENABLE EQU BIT29
CINTIRQ_ENABLE EQU BIT28
CINT_BIT EQU BIT27
BREAKPOINT EQU BIT24
; --------------------------
; Master Interrupt Registers
; --------------------------
FIQ EQU 0x90001000
IRQ EQU 0x90001400
; FIQ Status Constants
F_UART EQU BIT8
F_SDRAM EQU BIT7
F_RTC EQU BIT6
F_SRAM EQU BIT5
F_UENG EQU BIT4
F_CINT EQU BIT3
F_PCI EQU BIT2
; IRQ Status Constants
I_UART EQU BIT8
I_SDRAM EQU BIT7
I_UART_REV_A EQU BIT6
I_RTC EQU BIT6
I_SRAM EQU BIT5
I_UENG EQU BIT4
I_CINT EQU BIT3
I_PCI EQU BIT2
; ------------------------------
; GPIO Enable and data Registers
; ------------------------------
GPIO_EN EQU 0x90001800
GPIO_DATA EQU 0x90001C00
; ------------------------
; Real Time Clock Register
; ------------------------
RTC_DIV EQU 0x90002000
RTC_TINT EQU 0x90002400
RTC_TVAL EQU 0x90002800
RTC_CNTR EQU 0x90002C00
RTC_ALM EQU 0x90003000
; RTC_DIV Register Constant
RTC_IRQ_SELECT EQU BIT19
RTC_INT_RESET EQU BIT18
RTC_INT_ENABLE EQU BIT17
RTC_WRITE_ENABLE EQU BIT16
; ----
; UART
; ----
UART_SR EQU 0x90003400
UART_CR EQU 0x90003800
UART_DR EQU 0x90003C00
; UART Status Register Constants
UART_TX_FIFO_FULL EQU BIT7
UART_RX_FIFO_FULL EQU BIT6
UART_TX_FIFO_EMPTY EQU BIT5
UART_RX_READY EQU BIT4
UART_RX_OVERRUN EQU BIT3
UART_TX_READY EQU BIT2
UART_FRAMING_ERR EQU BIT1
UART_PARITY_ERR EQU BIT0
; UART Control Register Contants
UART_INT_SELECT EQU BIT9
UART_INT_CLEAR EQU BIT9
UART_TX_INT_ENABLE EQU BIT8
UART_ENABLE_BIT EQU BIT7
UART_DATA_BITS_8 EQU (BIT6 | BIT5)
UART_RX_INT_ENABLE EQU BIT4
UART_STOP_BIT_1 EQU BIT3
UART_PARITY_ENABLE EQU BIT1
UART_BREAK EQU BIT0
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