interrupts.h

ucos on sa1200 from ixp1200 EB

/* interrupts.h
 *
 *------------------------------------------------------------
 *                                                                      
 *                  I N T E L   P R O P R I E T A R Y                   
 *                                                                      
 *     COPYRIGHT (c)  1998-1999 BY  INTEL  CORPORATION.  ALL RIGHTS          
 *     RESERVED.   NO  PART  OF THIS PROGRAM  OR  PUBLICATION  MAY      
 *     BE  REPRODUCED,   TRANSMITTED,   TRANSCRIBED,   STORED  IN  A    
 *     RETRIEVAL SYSTEM, OR TRANSLATED INTO ANY LANGUAGE OR COMPUTER    
 *     LANGUAGE IN ANY FORM OR BY ANY MEANS, ELECTRONIC, MECHANICAL,    
 *     MAGNETIC,  OPTICAL,  CHEMICAL, MANUAL, OR OTHERWISE,  WITHOUT    
 *     THE PRIOR WRITTEN PERMISSION OF :                                
 *                                                                      
 *                        INTEL  CORPORATION                            
 *                                                                     
 *                     2200 MISSION COLLEGE BLVD                        
 *                                                                      
 *               SANTA  CLARA,  CALIFORNIA  95052-8119                  
 *                                                                      
 *------------------------------------------------------------
 * system: SA1200
 * subsystem: SA1200 ARM Core
 * author: Henry Qian 02/22/99
 * revisions:
 *
 */
/*
 * Dan M. White - 10/13/00 - added SAr_PutCPSR for bug #1112 (cpsr not saved)
 *
 */

#ifndef INTERRUPTS_H
#define INTERRUPTS_H

typedef enum {
    RESERVED_00         = 0,
    SOFT                = 1,
    RESERVED_02         = 2,
    RESERVED_03         = 3,
    TIMER1              = 4,
    TIMER2              = 5,
    TIMER3              = 6,
    TIMER4              = 7,
    RESERVED_08         = 8,
    EXTERNAL_C_PIN      = 9,
    MICRO_THREAD        = 10,
    SRAM_MEMORY         = 11,
    SERIAL              = 12,
    SDRAM_MEMORY        = 13,
    REAL_TIME_CLOCK     = 14,
    PCI_DOORBELL        = 15,
    DMA1                = 16,
    DMA2                = 17,
    PCI_IRQ_L           = 18,
    RESERVED_19         = 19,
    DMA1_NOT_BUSY       = 20,
    DMA2_NOT_BUSY       = 21,
    START_BIST          = 22,
    SERR                = 23,
    SDRAM_PARITY        = 24,
    I2O_INPOST          = 25,
    RESERVED_26         = 26,
    DISCARD_TIMER       = 27,
    DATA_PARITY         = 28,
    PCI_MASTER_ABORT    = 29,
    PCI_TARGET_ABORT    = 30,
    PCI_PARITY          = 31,
    MAX_NUM_OF_SOURCES
} IntSource;

#define SA_SUCCESS 0
#define SA_FAIL 1

#define NOINT   0xC0
#define IRQ_INT 0x80
#define FIQ_INT 0x40

#define IRQ_VECTOR 0x00000038
#define FIQ_VECTOR 0x0000003C
#define ALL_BITS 0xFFFFFFFF

// Pointer to function with an integer argument returning void
typedef void (*PFVI)(int);

typedef struct {
    PFVI func;
    int data;
} IntHandler;

#ifdef __cplusplus
extern "C" {
#endif

/* Master Interrupt Disable/Enable routines */
unsigned int SAr_DisableInt(void);
void SAr_EnableInt(unsigned int);


// -----------------------
// Regular Interrupt (IRQ)
// -----------------------
void SA_InitIRQ(void);
IntHandler SA_IRQ_Connect(  IntSource intSource,
                            PFVI intServiceRoutine,
                            int userParam);
int SA_IRQ_Dispatcher(void);
int SA_IRQ_Enable(IntSource intSource);
int SA_IRQ_Disable(IntSource intSource);
void SAr_DisableAllIRQs(void);
void SA_IRQ_InitDoorBell(PFVI intServiceRoutine);
void SA_IRQ_InitSoft(PFVI intServiceRoutine);
void SAir_IRQTrapWrap(void);
// --------------------
// Fast Interrupt (FIQ)
// --------------------
void SA_InitFIQ(void);
IntHandler SA_FIQ_Connect(  IntSource intSource,
                            PFVI intServiceRoutine,
                            int userParam);
void SA_FIQ_Dispatcher(void);
int SA_FIQ_Enable(IntSource intSource);
int SA_FIQ_Disable(IntSource intSource);
void SAr_DisableAllFIQs(void);
void SA_FIQ_InitDoorBell(PFVI intServiceRoutine);
void SA_FIQ_InitSoft(PFVI intServiceRoutine);
void SAir_FIQTrapWrap(void);


void SA_InitSysTimer(void);

unsigned int SAr_GetCPSR(void);     /* get current processor status reg */
unsigned int SAr_PutCPSR(unsigned int);     /* put current processor status reg */
void SAr_OsNotUseUART(void);
void SAr_OsUseUART(void);
    
#ifdef __cplusplus
}
#endif

__swi(0x123456) void enterSWI(int);
#define ENTER_SVC enterSWI(0x17)

#define EXIT_SVC __asm { SUBS pc, pc, #0 } // move SPSR -> CPSR

#endif // INTERRUPTS_H

// end of file