platform.h

ucos on sa1200 from ixp1200 EB

/* Clock frequency for UART */
#ifdef SA1200_A0
#define UART_CLOCK                      100000000/32
#else
#define UART_CLOCK                      3686400
#endif

#define BAUD_9600                       (((UART_CLOCK/16/9600)-1)   << 16)
#define BAUD_19200                      (((UART_CLOCK/16/19200)-1)  << 16)
#define BAUD_38400                      (((UART_CLOCK/16/38400)-1)  << 16)
#define BAUD_57600                      (((UART_CLOCK/16/57600)-1)  << 16)
#define BAUD_115200                     (((UART_CLOCK/16/115200)-1) << 16)

#define CLEAR_BAUD_RATE_FIELD           (0x3FF << 16)

/* UART Data Register with Error Status */
#define UART_DATA_FRMING_ERR            BIT10
#define UART_DATA_RX_OVERRUN            BIT9
#define UART_DATA_PARITY_ERR            BIT8

/* ---------------- */
/* PCI Control Unit */
/* ---------------- */
#define CSR_BASE                        0x42000000

#define PCI_VENDOR_ID                   0x00
#define PCI_DEVICE_ID                   0x02
#define PCI_COMMAND                     0x04
#define PCI_STATUS                      0x06
#define PCI_REV_ID                      0x08
#define PCI_CLASS_ID                    0x09
#define PCI_LATENCY                     0x0D
#define PCI_MEM_BAR                     0x10
#define PCI_CSR_BAR                     0x10
#define PCI_IO_BAR                      0x14
#define PCI_DRAM_BAR                    0x18
#define PCI_OUT_INT_STATUS              0x30
#define PCI_OUT_INT_MASK                0x34
#define PCI_INT_LINE                    0x3C
#define MAILBOX_0                       0x50
#define MAILBOX_1                       0x54
#define MAILBOX_2                       0x58
#define MAILBOX_3                       0x5C
#define DOORBELL                        0x60
#define DOORBELL_SETUP                  0x64
#define ROM_BYTE_WRITE                  0x68
#define CAP_PTR_EXT                     0x70
#define PWR_MGMT                        0x74
#define PCI_RESET                       0x7C
#define CHAN_1_BYTE_COUNT               0x80
#define CHAN_1_PCI_ADDR                 0x84
#define CHAN_1_DRAM_ADDR                0x88
#define CHAN_1_DESC_PTR                 0x8C
#define CHAN_1_CONTROL                  0x90
#define DMA_INF_MODE                    0x9C
#define CHAN_2_BYTE_COUNT               0xA0
#define CHAN_2_PCI_ADDR                 0xA4
#define CHAN_2_DRAM_ADDR                0xA8
#define CHAN_2_DESC_PTR                 0xAC
#define CHAN_2_CONTROL                  0xB0
#define CSR_BASE_ADDR_MASK              0xF8
//#define CSR_BASE_ADDR_OFF               0xFC
#define DRAM_BASE_ADDR_MASK             0x100
//#define DRAM_BASE_ADDR_OFF              0x104
#define ROM_BASE_ADDR_MASK              0x108
//#define DRAM_TIMING                     0x10C
//#define DRAM_ADDR_SIZE_0                0x110
//#define DRAM_ADDR_SIZE_1                0x114
//#define DRAM_ADDR_SIZE_2                0x118
//#define DRAM_ADDR_SIZE_3                0x11C
#define I2O_IFH                         0x120
#define I2O_IPT                         0x124
#define I2O_OPH                         0x128
#define I2O_OFT                         0x12C
#define I2O_IFC                         0x130
#define I2O_OPC                         0x134
#define I2O_IPC                         0x138
#define SA_CONTROL                      0x13C
#define PCI_ADDR_EXT                    0x140
#define PREFETCH_RANGE                  0x144
#define PCI_ABITOR_STATUS               0x148
#define DBELL_PCI_MASK                  0x150
#define DBELL_SA_MASK                   0x154
#define IRQ_STATUS                      0x180 
#define IRQ_RAW_STATUS                  0x184 
#define IRQ_ENABLE                      0x188 
#define IRQ_ENABLE_SET                  0x188 
#define IRQ_ENABLE_CLEAR                0x18C 
#define IRQ_SOFT                        0x190 
#define FIQ_STATUS                      0x280 
#define FIQ_RAW_STATUS                  0x284 
#define FIQ_ENABLE                      0x288 
#define FIQ_ENABLE_SET                  0x288 
#define FIQ_ENABLE_CLEAR                0x28C 
#define FIQ_SOFT                        0x290 
#define TIMER_1_LOAD                    0x300 
#define TIMER_1_VALUE                   0x304 
#define TIMER_1_CONTROL                 0x308 
#define TIMER_1_CLEAR                   0x30C 
#define TIMER_2_LOAD                    0x320 
#define TIMER_2_VALUE                   0x324 
#define TIMER_2_CONTROL                 0x328 
#define TIMER_2_CLEAR                   0x32C 
#define TIMER_3_LOAD                    0x340 
#define TIMER_3_VALUE                   0x344 
#define TIMER_3_CONTROL                 0x348 
#define TIMER_3_CLEAR                   0x34C 
#define TIMER_4_LOAD                    0x360 
#define TIMER_4_VALUE                   0x364 
#define TIMER_4_CONTROL                 0x368 
#define TIMER_4_CLEAR                   0x36C 

/* ---------------------------- */
/* PCI_RESET Register Constants */
/* ---------------------------- */

#define UENG0_RST                       BIT0
#define UENG1_RST                       BIT1
#define UENG2_RST                       BIT2
#define UENG3_RST                       BIT3
#define UENG4_RST                       BIT4
#define UENG5_RST                       BIT5
#define PCIRST_RST                      BIT14
#define EXT_RST                         BIT15
#define FXCMD_RST                       BIT17
#define FBI_RST                         BIT16
#define SDRAM_RST                       BIT18
#define SRAM_RST                        BIT29
#define PCI_RST                         BIT30
#define SACORE_RST                      BIT31

/* ------------------------------ */
/* ARM control register constants */
/* ------------------------------ */
#define INIT_COMPLETE                   BIT0
#define PCI_NRESET                      BIT9
#define PCI_CFN                         BIT31
#define ROM_TIMING                      0x0fff0000
#define ROM_SETUP                       0x04aa0000
#define SA_CTL_COMPLETE                 (INIT_COMPLETE | PCI_NRESET)

/* --------------- */
/* Interrupt Flags */
/* --------------- */
#define SOFT_INT                        BIT1
#define TIMER1_INT                      BIT4
#define TIMER2_INT                      BIT5
#define TIMER3_INT                      BIT6
#define TIMER4_INT                      BIT7
#define DOORBELL_INT                    BIT15
#define DMA1_INT                        BIT16
#define DMA2_INT                        BIT17
#define PCI_IRQ_L_INT                   BIT18
#define DMA1_NOT_BUSY_INT               BIT20
#define DMA2_NOT_BUSY_INT               BIT21
#define START_BIST_INT                  BIT22
#define SERR_INT                        BIT23
#define SDRAM_PARITY_INT                BIT24
#define I2O_INPOST_INT                  BIT25
#define DISCARD_TIMER_INT               BIT27
#define DATA_PARITY_INT                 BIT28
#define PCI_MASTER_ABORT_INT            BIT29
#define PCI_TARGET_ABORT_INT            BIT30
#define PCI_PARITY_INT                  BIT31

/* ------------------------------- */
/* Timer Control Register Constant */
/* ------------------------------- */
#define TIMER_ENABLE                    BIT7
#define TIMER_MODE                      BIT6

/*  timer stuff:
 *  On SA1200 there is an external clock which ticks at 3.68Mhz. This is wired
 *  into the DC21285 chip's timer #3. There are 24 bits of counter that we can
 *  set to divide this external timer down. Each external tick is 3.68*(10**-6)
 *  seconds long, 1mSEC needs counter of 3680 (every 3680 external ticks, we
 *  get one clock interrupt).
 */

#define OS_TIMER                        3
 /*
 the following timers vary depending on board rev, so,
 they are made into variables in interrupts.c
 varying on IXP1200_SysCpuRev.
*/
/*
#ifdef SA1200_A0
#define mSEC_1                          100000000/1000
#else
//#define mSEC_1                          162200000/1000
#define mSEC_1                          165890000/1000
#endif

#define mSEC_5                          (mSEC_1 * 5)
#define mSEC_10                         (mSEC_1 * 10)
#define mSEC_100                        (mSEC_1 * 100)
#define SEC_1                           (mSEC_1 * 1000)
#define SEC_10                          (SEC_1  * 10)
*/
/* ---------------------------------- */
/* Translation Lookaside Buffer Table */
/* ---------------------------------- */
#define TTB_SIZE                        SZ_32K

/* -------------- */
/* CoProcessor 15 */
/* -------------- */
#define IC_ON                           BIT12
#define DC_ON                           BIT2
#define WB_ON                           BIT3


/* -------------- */
/* SRAM Registers */
/* -------------- */

#define SRAM_CSR                        0x38000000 /* SRAM CSR */
#define SRAM_SLOW_CONFIG                0x38000020 /* SRAM Flash/Mac cycle times */
#define SRAM_FLASH_CONFIG               0x38000024 /* Flash timing */
#define SRAM_MAC_CONFIG                 0x38000028 /* Mac timing */
#define SRAM_SLOW_CONFIG_V_165          0x00001852
#define SRAM_SLOPORT_CFG_V_165          0x454B0E07

/* ------------------ */
/* SRAM CSR constants */
/* ------------------ */

#define SRAM_RLK                        BIT20   /* Read lock order bit */
#define SRAM_RDY                        BIT19   /* Slow port ready enable */
#define SRAM_CFT                        BIT18   /* Comand FIFO Test Enable */
#define SRAM_MAC                        BIT17   /* MAC Configuration */
#define SRAM_FLWT                       BIT16   /* Flowthrough SRAM Enable */
#define SRAM_BKW                        BIT15   /* Bank Switch Wait Enable */
#define SRAM_8MF                        BIT14   /* 8MB Flash */
#define SRAM_4MF                        BIT13   /* 4MB Flash */
#define SRAM_2MF                        BIT12   /* 2MB Flash */
#define SRAM_8MSR                       BIT11   /* 8MB SRAM */
#define SRAM_4MSR                       BIT10   /* 4MB SRAM */
#define SRAM_2MSR                       BIT9    /* 2MB SRAM */
#define SRAM_1MSR                       BIT8    /* 1MB SRAM */
#define SRAM_RLAM                       BIT4    /* ASB Read Lock Achieved Mask */
#define SRAM_IRQ                        BIT3    /* IRQ Enable */
#define SRAM_FIQ                        BIT2    /* FIQ Enable */
#define SRAM_RLRS                       BIT1    /* ASB Read Lock Retry Achieved Status */
#define SRAM_RLS                        BIT0    /* ASB Read Lock Achieved Status */

/* --------------- */
/* SDRAM Registers */
/* --------------- */

#define SDRAM_CSR                       0xFF000000 /* SDRAM CSR */
#define SDRAM_MEMCTL0                   0xFF000004 /* SDRAM timing info */
#define SDRAM_MEMCTL1                   0xFF000008 /* SDRAM timing info */
#define SDRAM_MEMINIT                   0xFF00000C /* SDRAM initialization timing */

/* ------------------- */
/* SDRAM CSR Constants */
/* ------------------- */

#define SDRAM_EN_FTST                   BIT15   /* Enable FIFO RAM test */
#define SDRAM_EN_INT                    BIT10   /* Enable Parity Interrupt */
#define SDRAM_EN_IRQ                    BIT9    /* Select IRQ */
#define SDRAM_EN_FIQ                    BIT8    /* Select FIQ */
#define SDRAM_EN_CPE                    BIT6    /* Enable StrongARM Core parity error */
#define SDRAM_EN_PCIPE                  BIT5    /* Enable PCI parity error */
#define SDRAM_EN_UEPE                   BIT4    /* Enable Microengine parity error */
#define SDRAM_GENPAR                    BIT3    /* Enable parity generation */
#define SDRAM_EVENPAR                   BIT2    /* Generate even parity */
#define SDRAM_TF_BENDN                  BIT1    /* 1 = big endian mode */
#define SDRAM_INIT                      BIT0    /* Initialize SDRAM unit */
#define SDRAM_CSR_VALUE (SDRAM_INIT)
    

/* These are VxWorks specific.  It comes from VxWorks file ebsa285.h */
/* One VxWorks porting is done.  It should get from there */

/* interrupt levels */
#define INT_LVL_SOFT		1	/* soft interrupt */
#define INT_LVL_AMBARX		2	/* AMBA serial port Rx */
#define INT_LVL_AMBATX		3	/* AMBA serial port Tx */
#define INT_LVL_TIMER_1 	4	/* timer 1 */
#define INT_LVL_TIMER_2 	5	/* timer 2 */
#define INT_LVL_TIMER_3 	6	/* timer 3 */
#define INT_LVL_TIMER_4 	7	/* timer 4 */
#define	INT_LVL_IRQ_IN_0	8	/* external to 21285 */
#define	INT_LVL_IRQ_IN_1	9	/* external to 21285 */
#define	INT_LVL_IRQ_IN_2	10	/* external to 21285 */
#define	INT_LVL_IRQ_IN_3	11	/* external to 21285 */
#define INT_LVL_SPIO		12	/* Super I/O serial ports */
#define INT_LVL_DOORBELL	15	/* PCI doorbell -- Henry Qian 11/04/98 */
#define	INT_LVL_PCI		18	/* PCI external interrupts */

#endif /* __address_h */

/* end of file */