📄 platform.h
字号:
/* platform.h
*
*------------------------------------------------------------
*
* I N T E L P R O P R I E T A R Y
*
* COPYRIGHT (c) 1999 BY INTEL CORPORATION. ALL RIGHTS
* RESERVED. NO PART OF THIS PROGRAM OR PUBLICATION MAY
* BE REPRODUCED, TRANSMITTED, TRANSCRIBED, STORED IN A
* RETRIEVAL SYSTEM, OR TRANSLATED INTO ANY LANGUAGE OR COMPUTER
* LANGUAGE IN ANY FORM OR BY ANY MEANS, ELECTRONIC, MECHANICAL,
* MAGNETIC, OPTICAL, CHEMICAL, MANUAL, OR OTHERWISE, WITHOUT
* THE PRIOR WRITTEN PERMISSION OF :
*
* INTEL CORPORATION
*
* 2200 MISSION COLLEGE BLVD
*
* SANTA CLARA, CALIFORNIA 95052-8119
*
*------------------------------------------------------------
* system: SA1200
* subsystem: UCOS
* author: Henry Qian 01/29/99
* revisions:
* Dan White
* 10/18/99 - added FLASH_SIZE
* 03/31/00 - Dan White - added Rev B0 changes
* 04/25/00 - Dan White - added 200 MHz changes
*
*
*/
#ifndef __address_h
#define __address_h 1
#define BIT0 0x00000001
#define BIT1 0x00000002
#define BIT2 0x00000004
#define BIT3 0x00000008
#define BIT4 0x00000010
#define BIT5 0x00000020
#define BIT6 0x00000040
#define BIT7 0x00000080
#define BIT8 0x00000100
#define BIT9 0x00000200
#define BIT10 0x00000400
#define BIT11 0x00000800
#define BIT12 0x00001000
#define BIT13 0x00002000
#define BIT14 0x00004000
#define BIT15 0x00008000
#define BIT16 0x00010000
#define BIT17 0x00020000
#define BIT18 0x00040000
#define BIT19 0x00080000
#define BIT20 0x00100000
#define BIT21 0x00200000
#define BIT22 0x00400000
#define BIT23 0x00800000
#define BIT24 0x01000000
#define BIT25 0x02000000
#define BIT26 0x04000000
#define BIT27 0x08000000
#define BIT28 0x10000000
#define BIT29 0x20000000
#define BIT30 0x40000000
#define BIT31 0x80000000
#define SZ_1K 0x00000400
#define SZ_4K 0x00001000
#define SZ_8K 0x00002000
#define SZ_16K 0x00004000
#define SZ_32K 0x00008000
#define SZ_64K 0x00010000
#define SZ_128K 0x00020000
#define SZ_256K 0x00040000
#define SZ_512K 0x00080000
#define SZ_1M 0x00100000
#define SZ_2M 0x00200000
#define SZ_4M 0x00400000
#define SZ_8M 0x00800000
#define SZ_16M 0x01000000
#define SZ_32M 0x02000000
#define SZ_64M 0x04000000
#define SZ_128M 0x08000000
#define SZ_256M 0x10000000
#define SZ_512M 0x20000000
#define SZ_1G 0x40000000
#define ALL_BITS 0xFFFFFFFF
/* -------------------------------- */
/* SA1200 physical memory addresses */
/* -------------------------------- */
#define ROMBase 0x00000000
#define ROMSize SZ_1M
#define SRAMBase 0x10000000
#define SRAMSize (SZ_512M + SZ_256M)
#define PCILocalBase 0x42000000
#define PCILocalSize SZ_1M
#define PCIConfigTypeOneBase 0x52000000
#define PCIConfigTypeOneSize SZ_32M
#define PCIConfigTypeZeroBase 0x53000000
#define PCIConfigTypeZeroSize SZ_32M
#define PCIIOBase 0x54000000
#define PCIIOSize SZ_1M
#define PCIMemBase 0x60000000
#define PCIMemSize SZ_512M
#define ARMCOREBase 0x90000000
#define ARMCORESize SZ_1M
#define AMBABase 0xB0000000
#define AMBASize SZ_1M
#define DRAMBaseForUEng 0xC0000000
#define DRAMBaseForUEngSize 0x01800000 /* 24Mb */
#define DRAMBase 0xC0000000
#define DRAMSize SZ_8M
#define DRAMPrefetchBase 0xD0000000
#define DRAMPrefetchSize DRAMSize
#define DRAMFlushBase 0xE0000000
#define DRAMFlushSize DRAMSize
#define DRAMControlBase 0xFF000000
#define DRAMControlSize SZ_1M
/* ---------------------------- */
/* MMU Virtual SA1200 Addresses */
/* ---------------------------- */
#define DRAM_BASE 0x00000000
#define DRAM_SIZE SZ_8M
#define ROM_BASE 0x08000000
#define ROM_SIZE SZ_1M
#define SRAM_BASE SRAMBase
#define SRAM_SIZE SZ_8M
#define FLASH_SIZE SZ_16K
/* ================ */
/* SA1200 REGISTERS */
/* ================ */
/* -------------------------- */
/* PLL Configuration Register */
/* -------------------------- */
#define PLL_CFG 0x90000C00
/* PLL_CFG Constants @ 3.6864 MHz */
#define PLL_A_CLK_29MHz 0x00
#define PLL_A_CLK_36MHz 0x01
#define PLL_A_CLK_44MHz 0x02
#define PLL_A_CLK_51MHz 0x03
#define PLL_A_CLK_58MHz 0x04
#define PLL_A_CLK_66MHz 0x05
#define PLL_A_CLK_73MHz 0x06
#define PLL_A_CLK_81MHz 0x07
#define PLL_A_CLK_88MHz 0x08
#define PLL_A_CLK_95MHz 0x09
#define PLL_A_CLK_103MHz 0x0A
#define PLL_A_CLK_110MHz 0x0B
#define PLL_A_CLK_117MHz 0x0C
#define PLL_A_CLK_132MHz 0x0D
#define PLL_A_CLK_147MHz 0x0E
#define PLL_A_CLK_154MHz 0x0F
#define PLL_A_CLK_162MHz 0x10
#define PLL_A_CLK_176MHz 0x11
#define PLL_A_CLK_191MHz 0x12
/* add parameters for fast clock rate an B0 */
#define PLL_CLK_29MHz 0x00
#define PLL_CLK_36MHz 0x01
#define PLL_CLK_44MHz 0x02
#define PLL_CLK_51MHz 0x03
#define PLL_CLK_58MHz 0x04
#define PLL_CLK_66MHz 0x05
#define PLL_CLK_73MHz 0x06
#define PLL_CLK_81MHz 0x07
#define PLL_CLK_88MHz 0x08
#define PLL_CLK_95MHz 0x09
#define PLL_CLK_103MHz 0x0A
#define PLL_CLK_110MHz 0x0B
#define PLL_CLK_132MHz 0x0C
#define PLL_CLK_147MHz 0x0D
#define PLL_CLK_154MHz 0x0E
#define PLL_CLK_162MHz 0x0F
#define PLL_CLK_165MHz 0x10
#define PLL_CLK_176MHz 0x11
#define PLL_CLK_191MHz 0x12
#define PLL_CLK_200MHz 0x13
#define CCCR_INIT_VALUE (PLL_CLK_200MHz)
#define CCCR_INIT_VALUE_A (PLL_A_CLK_162MHz)
/* ------------------------------ */
/* FBI Control & Status Registers */
/* ------------------------------ */
#define IREG 0xB00401E0
/* IREG Contants */
#define UEFIQ_ENABLE BIT31
#define UEIRQ_ENABLE BIT30
#define CINTFIQ_ENABLE BIT29
#define CINTIRQ_ENABLE BIT28
#define CINT_BIT BIT27
#define BREAKPOINT BIT24
/* -------------------------- */
/* Master Interrupt Registers */
/* -------------------------- */
#define FIQ 0x90001000
#define IRQ 0x90001400
/* FIQ Status Constants */
#define F_UART BIT8
#define F_SDRAM BIT7
#define F_RTC BIT6
#define F_SRAM BIT5
#define F_UENG BIT4
#define F_CINT BIT3
#define F_PCI BIT2
/* IRQ Status Constants */
#define I_UART BIT8
#define I_SDRAM BIT7
#define I_UART_REV_A BIT6
#define I_RTC BIT6
#define I_SRAM BIT5
#define I_UENG BIT4
#define I_CINT BIT3
#define I_PCI BIT2
/* ------------------------------ */
/* GPIO Enable and data Registers */
/* ------------------------------ */
#define GPIO_EN 0x90001800
#define GPIO_DATA 0x90001C00
/* ------------------------ */
/* Real Time Clock Register */
/* ------------------------ */
#define RTC_DIV 0x90002000
#define RTC_TINT 0x90002400
#define RTC_TVAL 0x90002800
#define RTC_CNTR 0x90002C00
#define RTC_ALM 0x90003000
/* RTC_DIV Register Constant */
#define RTC_IRQ_SELECT BIT19 /* 1 means RTC will gen IRQ interrupt */
#define RTC_INT_RESET BIT18
#define RTC_INT_ENABLE BIT17
#define RTC_WRITE_ENABLE BIT16
/* ---- */
/* UART */
/* ---- */
#define UART_SR 0x90003400
#define UART_CR 0x90003800
#define UART_DR 0x90003C00
/* UART Status Register Constants */
#define UART_TX_FIFO_FULL BIT7
#define UART_RX_FIFO_FULL BIT6
#define UART_TX_FIFO_EMPTY BIT5
#define UART_RX_READY BIT4
#define UART_RX_OVERRUN BIT3
#define UART_TX_READY BIT2
#define UART_FRAMING_ERR BIT1
#define UART_PARITY_ERR BIT0
/* UART Control Register Contants */
#define UART_INT_CLEAR BIT9 /* Rev A */
#define UART_INT_SELECT BIT9 /* Rev B */
#define UART_TX_INT_ENABLE BIT8
#define UART_ENABLE_BIT BIT7
#define UART_DATA_BITS_8 (BIT6 | BIT5)
#define UART_RX_INT_ENABLE BIT4
#define UART_STOP_BIT_1 BIT3
#define UART_PARITY_ENABLE BIT1
#define UART_BREAK BIT0
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -