interrupts.c

ucos on sa1200 from ixp1200 EB

			else
				*(unsigned int*)(CSR_BASE + TIMER_4_CLEAR) = 0xFFFFFFFF;
        }

#if INT_NOT_USED
        if (PCI_FIQ_Status & DMA1_INT)
        {
            if (FIQ_Handlers[DMA1].func)
                (FIQ_Handlers[DMA1].func)(FIQ_Handlers[DMA1].data);
        }

        if (PCI_FIQ_Status & DMA2_INT)
        {
            if (FIQ_Handlers[DMA2].func)
                (FIQ_Handlers[DMA2].func)(FIQ_Handlers[DMA2].data);
        }

        if (PCI_FIQ_Status & PCI_IRQ_L_INT)
        {
            if (FIQ_Handlers[PCI_IRQ_L].func)
                (FIQ_Handlers[PCI_IRQ_L].func)(FIQ_Handlers[PCI_IRQ_L].data);
        }

        if (PCI_FIQ_Status & DMA1_NOT_BUSY_INT)
        {
            if (FIQ_Handlers[DMA1_NOT_BUSY].func)
                (FIQ_Handlers[DMA1_NOT_BUSY].func)(FIQ_Handlers[DMA1_NOT_BUSY].data);
        }

        if (PCI_FIQ_Status & DMA2_NOT_BUSY_INT)
        {
            if (FIQ_Handlers[DMA2_NOT_BUSY].func)
                (FIQ_Handlers[DMA2_NOT_BUSY].func)(FIQ_Handlers[DMA2_NOT_BUSY].data);
        }

        if (PCI_FIQ_Status & START_BIST_INT)
        {
            if (FIQ_Handlers[START_BIST].func)
                (FIQ_Handlers[START_BIST].func)(FIQ_Handlers[START_BIST].data);
        }

        if (PCI_FIQ_Status & SERR_INT)
        {
            if (FIQ_Handlers[SERR].func)
                (FIQ_Handlers[SERR].func)(FIQ_Handlers[SERR].data);
        }

        if (PCI_FIQ_Status & SDRAM_PARITY_INT)
        {
            if (FIQ_Handlers[SDRAM_PARITY].func)
                (FIQ_Handlers[SDRAM_PARITY].func)(FIQ_Handlers[SDRAM_PARITY].data);
        }

        if (PCI_FIQ_Status & I2O_INPOST_INT)
        {
            if (FIQ_Handlers[I2O_INPOST].func)
                (FIQ_Handlers[I2O_INPOST].func)(FIQ_Handlers[I2O_INPOST].data);
        }

        if (PCI_FIQ_Status & DISCARD_TIMER_INT)
        {
            if (FIQ_Handlers[DISCARD_TIMER].func)
                (FIQ_Handlers[DISCARD_TIMER].func)(FIQ_Handlers[DISCARD_TIMER].data);
        }

        if (PCI_FIQ_Status & DATA_PARITY_INT)
        {
            if (FIQ_Handlers[DATA_PARITY].func)
                (FIQ_Handlers[DATA_PARITY].func)(FIQ_Handlers[DATA_PARITY].data);
        }

        if (PCI_FIQ_Status & PCI_MASTER_ABORT_INT)
        {
            if (FIQ_Handlers[PCI_MASTER_ABORT].func)
                (FIQ_Handlers[PCI_MASTER_ABORT].func)(FIQ_Handlers[PCI_MASTER_ABORT].data);
        }

        if (PCI_FIQ_Status & PCI_TARGET_ABORT_INT)
        {
            if (FIQ_Handlers[PCI_TARGET_ABORT].func)
                (FIQ_Handlers[PCI_TARGET_ABORT].func)(FIQ_Handlers[PCI_TARGET_ABORT].data);
        }

        if (PCI_FIQ_Status & PCI_PARITY_INT)
        {
            if (FIQ_Handlers[PCI_PARITY].func)
                (FIQ_Handlers[PCI_PARITY].func)(FIQ_Handlers[PCI_PARITY].data);
        }
#endif // #if INT_NOT_USED
    }
}


/*
**  int SA_FIQ_Enable(IntSource intSource)
**  int SA_FIQ_Disable(IntSource intSource)
**
**  DESCRIPTION
**      Enable/disable a FIQ interrupt.
** 
**  RETURNS
**      success:    SA_SUCCESS
**      error:      SA_FAIL
*/
int SA_FIQ_Enable(IntSource intSource)
{
    int retval = SA_SUCCESS;

    unsigned int origIntMask = SAr_DisableInt();

    switch (intSource)
    {
        case MICRO_THREAD:
            *(unsigned int*)IREG = (*(unsigned int*)IREG | UEFIQ_ENABLE) & 0xF0000000;
            break;

        case EXTERNAL_C_PIN:
            *(unsigned int*)IREG = (*(unsigned int*)IREG | CINTFIQ_ENABLE) & 0xF0000000;
            break;

        case REAL_TIME_CLOCK:
            *(unsigned int*)RTC_DIV |= (RTC_INT_ENABLE | RTC_WRITE_ENABLE);
            break;

        case SRAM_MEMORY:
            *(unsigned int*)SRAM_CSR =
                (*(unsigned int*)SRAM_CSR | SRAM_FIQ) & 0xFFFFFFFC;
            break;

        case SDRAM_MEMORY:
            *(unsigned int*)SDRAM_CSR |= (SDRAM_EN_INT | SDRAM_EN_FIQ);
            break;

        case PCI_DOORBELL:
            pciCsrWr((void *)(CSR_BASE + FIQ_ENABLE_SET),(unsigned int)DOORBELL_INT);
            break;

        case SOFT:
            pciCsrWr((void *)(CSR_BASE + FIQ_ENABLE_SET),(unsigned int)SOFT_INT);
            break;

        case TIMER1:
            pciCsrWr((void *)(CSR_BASE + FIQ_ENABLE_SET),(unsigned int)TIMER1_INT);
            break;

        case TIMER2:
            pciCsrWr((void *)(CSR_BASE + FIQ_ENABLE_SET),(unsigned int)TIMER2_INT);
            break;

        case TIMER3:
            pciCsrWr((void *)(CSR_BASE + FIQ_ENABLE_SET),(unsigned int)TIMER3_INT);
            break;

        case TIMER4:
            pciCsrWr((void *)(CSR_BASE + FIQ_ENABLE_SET),(unsigned int)TIMER4_INT);
            break;

        case DMA1:
            pciCsrWr((void *)(CSR_BASE + FIQ_ENABLE_SET),(unsigned int)DMA1_INT);
            break;

        case DMA2:
            pciCsrWr((void *)(CSR_BASE + FIQ_ENABLE_SET),(unsigned int)DMA2_INT);
            break;

        case PCI_IRQ_L:
            pciCsrWr((void *)(CSR_BASE + FIQ_ENABLE_SET),(unsigned int)PCI_IRQ_L_INT);
            break;

        case DMA1_NOT_BUSY:
            pciCsrWr((void *)(CSR_BASE + FIQ_ENABLE_SET),(unsigned int)DMA1_NOT_BUSY_INT);
            break;

        case DMA2_NOT_BUSY:
            pciCsrWr((void *)(CSR_BASE + FIQ_ENABLE_SET),(unsigned int)DMA2_NOT_BUSY_INT);
            break;

        case START_BIST:
            pciCsrWr((void *)(CSR_BASE + FIQ_ENABLE_SET),(unsigned int)START_BIST_INT);
            break;

        case SERR:
            pciCsrWr((void *)(CSR_BASE + FIQ_ENABLE_SET),(unsigned int)SERR_INT);
            break;

        case SDRAM_PARITY:
            pciCsrWr((void *)(CSR_BASE + FIQ_ENABLE_SET),(unsigned int)SDRAM_PARITY_INT);
            break;

        case I2O_INPOST:
            pciCsrWr((void *)(CSR_BASE + FIQ_ENABLE_SET),(unsigned int)I2O_INPOST_INT);
            break;

        case DISCARD_TIMER:
            pciCsrWr((void *)(CSR_BASE + FIQ_ENABLE_SET),(unsigned int)DISCARD_TIMER_INT);
            break;

        case DATA_PARITY:
            pciCsrWr((void *)(CSR_BASE + FIQ_ENABLE_SET),(unsigned int)DATA_PARITY_INT);
            break;

        case PCI_MASTER_ABORT:
            pciCsrWr((void *)(CSR_BASE + FIQ_ENABLE_SET),(unsigned int)PCI_MASTER_ABORT_INT);
            break;

        case PCI_TARGET_ABORT:
            pciCsrWr((void *)(CSR_BASE + FIQ_ENABLE_SET),(unsigned int)PCI_TARGET_ABORT_INT);
            break;

        case PCI_PARITY:
            pciCsrWr((void *)(CSR_BASE + FIQ_ENABLE_SET),(unsigned int)PCI_PARITY_INT);
            break;

        default:
            retval = SA_FAIL;
            break;
    }

    SAr_EnableInt(origIntMask);

    return(retval);
}


int SA_FIQ_Disable(IntSource intSource)
{
    int retval = SA_SUCCESS;

    unsigned int origIntMask = SAr_DisableInt();

    switch (intSource)
    {
        case MICRO_THREAD:
            *(unsigned int*)IREG =
                (*(unsigned int*)IREG & ~UEFIQ_ENABLE) & 0xF0000000;
            break;

        case EXTERNAL_C_PIN:
            *(unsigned int*)IREG =
                (*(unsigned int*)IREG & ~CINTFIQ_ENABLE) & 0xF0000000;
            break;

        case REAL_TIME_CLOCK:
			*(unsigned int*)RTC_DIV =
			   (*(unsigned int*)RTC_DIV & ~RTC_INT_ENABLE) | RTC_WRITE_ENABLE;
            break;

        case SRAM_MEMORY:
            *(unsigned int*)SRAM_CSR =
                (*(unsigned int*)SRAM_CSR & ~SRAM_FIQ) & 0xFFFFFFFC;
            break;

        case SDRAM_MEMORY:
            *(unsigned int*)SDRAM_CSR &= ~SDRAM_EN_FIQ;
            break;

        case PCI_DOORBELL:
            pciCsrWr((void *)(CSR_BASE + FIQ_ENABLE_CLEAR),(unsigned int)DOORBELL_INT);
            break;

        case SOFT:
            pciCsrWr((void *)(CSR_BASE + FIQ_ENABLE_CLEAR),(unsigned int)SOFT_INT);
            break;

        case TIMER1:
            pciCsrWr((void *)(CSR_BASE + FIQ_ENABLE_CLEAR),(unsigned int)TIMER1_INT);
            break;

        case TIMER2:
            pciCsrWr((void *)(CSR_BASE + FIQ_ENABLE_CLEAR),(unsigned int)TIMER2_INT);
            break;

        case TIMER3:
            pciCsrWr((void *)(CSR_BASE + FIQ_ENABLE_CLEAR),(unsigned int)TIMER3_INT);
            break;

        case TIMER4:
            pciCsrWr((void *)(CSR_BASE + FIQ_ENABLE_CLEAR),(unsigned int)TIMER4_INT);
            break;

        case DMA1:
            pciCsrWr((void *)(CSR_BASE + FIQ_ENABLE_CLEAR),(unsigned int)DMA1_INT);
            break;

        case DMA2:
            pciCsrWr((void *)(CSR_BASE + FIQ_ENABLE_CLEAR),(unsigned int)DMA2_INT);
            break;

        case PCI_IRQ_L:
            pciCsrWr((void *)(CSR_BASE + FIQ_ENABLE_CLEAR),(unsigned int)PCI_IRQ_L_INT);
            break;

        case DMA1_NOT_BUSY:
            pciCsrWr((void *)(CSR_BASE + FIQ_ENABLE_CLEAR),(unsigned int)DMA1_NOT_BUSY_INT);
            break;

        case DMA2_NOT_BUSY:
            pciCsrWr((void *)(CSR_BASE + FIQ_ENABLE_CLEAR),(unsigned int)DMA2_NOT_BUSY_INT);
            break;

        case START_BIST:
            pciCsrWr((void *)(CSR_BASE + FIQ_ENABLE_CLEAR),(unsigned int)START_BIST_INT);
            break;

        case SERR:
            pciCsrWr((void *)(CSR_BASE + FIQ_ENABLE_CLEAR),(unsigned int)SERR_INT);
            break;

        case SDRAM_PARITY:
            pciCsrWr((void *)(CSR_BASE + FIQ_ENABLE_CLEAR),(unsigned int)SDRAM_PARITY_INT);
            break;

        case I2O_INPOST:
            pciCsrWr((void *)(CSR_BASE + FIQ_ENABLE_CLEAR),(unsigned int)I2O_INPOST_INT);
            break;

        case DISCARD_TIMER:
            pciCsrWr((void *)(CSR_BASE + FIQ_ENABLE_CLEAR),(unsigned int)DISCARD_TIMER_INT);
            break;

        case DATA_PARITY:
            pciCsrWr((void *)(CSR_BASE + FIQ_ENABLE_CLEAR),(unsigned int)DATA_PARITY_INT);
            break;

        case PCI_MASTER_ABORT:
            pciCsrWr((void *)(CSR_BASE + FIQ_ENABLE_CLEAR),(unsigned int)PCI_MASTER_ABORT_INT);
            break;

        case PCI_TARGET_ABORT:
            pciCsrWr((void *)(CSR_BASE + FIQ_ENABLE_CLEAR),(unsigned int)PCI_TARGET_ABORT_INT);
            break;

        case PCI_PARITY:
            pciCsrWr((void *)(CSR_BASE + FIQ_ENABLE_CLEAR),(unsigned int)PCI_PARITY_INT);
            break;

        default:
            retval = SA_FAIL;
            break;
    }

    SAr_EnableInt(origIntMask);

    return(retval);
}


/*
**  void SA_FIQ_InitDoorBell()
**
**  DESCRIPTION
**      Initialize doorbell register.
**      Hook up an interrupt service routine to
**      doorbell register.
**      Enable doorbell interrupt.
** 
**  RETURNS
**      None.
*/
void SA_FIQ_InitDoorBell(PFVI intServiceRoutine)
{
    SA_FIQ_Disable(PCI_DOORBELL);

    // Setup doorbell register's directions
    //
	pciCsrWr((void *)(CSR_BASE + DBELL_PCI_MASK),(unsigned int)0);
	pciCsrWr((void *)(CSR_BASE + DBELL_SA_MASK),(unsigned int)0xFFFFFFFF);

	pciCsrWr((void *)(CSR_BASE + DOORBELL_SETUP),(unsigned int)0xFFFFFFFF);


    SA_FIQ_Connect(PCI_DOORBELL, intServiceRoutine, 0);

    SA_FIQ_Enable(PCI_DOORBELL);
}


/*
**  void SA_FIQ_InitSoft()
**
**  DESCRIPTION
**      Hook up an interrupt service routine to
**      soft interrupt.
**      Enable soft interrupt.
** 
**  RETURNS
**      None.
*/
void SA_FIQ_InitSoft(PFVI intServiceRoutine)
{
    SA_FIQ_Disable(SOFT);
    SA_FIQ_Connect(SOFT, intServiceRoutine, 0);
    SA_FIQ_Enable(SOFT);
}




/*
**  void SAr_DisableAllIRQs()
**  void SAr_DisableAllFIQs()
**
**  DESCRIPTION
**      Disable all the interrupts IRQ & FIQ.
** 
**  RETURNS
**      None.
*/
void SAr_DisableAllIRQs(void)
{
    unsigned int origIntMask = SAr_DisableInt();

    *(unsigned int*)IREG &= ~(UEIRQ_ENABLE + CINTIRQ_ENABLE);
	if (*(unsigned int*)RTC_DIV & RTC_IRQ_SELECT)
	{
		*(unsigned int*)RTC_DIV =
		   (*(unsigned int*)RTC_DIV & ~RTC_INT_ENABLE) | RTC_WRITE_ENABLE;
	}
    *(unsigned int*)UART_CR = 0;
    pciCsrWr((void *)(CSR_BASE + IRQ_ENABLE_CLEAR),(unsigned int)ALL_BITS);

    *(unsigned int*)SRAM_CSR &= ~SRAM_IRQ;
    *(unsigned int*)SDRAM_CSR &= ~SDRAM_EN_IRQ;

    SAr_EnableInt(origIntMask);
}

void SAr_DisableAllFIQs(void)
{
    unsigned int origIntMask = SAr_DisableInt();

    *(unsigned int*)IREG &= ~(UEFIQ_ENABLE + CINTFIQ_ENABLE);
    pciCsrWr((void *)(CSR_BASE + FIQ_ENABLE_CLEAR),(unsigned int)ALL_BITS);
	if (!(*(unsigned int*)RTC_DIV & RTC_IRQ_SELECT))
	{
		*(unsigned int*)RTC_DIV =
		   (*(unsigned int*)RTC_DIV & ~RTC_INT_ENABLE) | RTC_WRITE_ENABLE;
	}
    SAr_EnableInt(origIntMask);
}


/*
**  void SAr_OsNotUseUART(void)
**  void SAr_OsUseUART(void)
**
**  DESCRIPTION
**      In the situation that OS works with Angel,
**      Angel has the whole control of the only UART.
**      When UART IRQ interrupt comes, OS need yield control to
**      Angel's ISR instead of processing it itself.
**
**      SAr_OsUseUART() let user have a choice later not to use Angel,
**      and return UART control back to OS.
** 
**  RETURNS
**      None.
*/
unsigned int SAv_OsNotUseUART = 0;

void SAr_OsNotUseUART(void)
{
    SAv_OsNotUseUART = 1;
}

void SAr_OsUseUART(void)
{
    SAv_OsNotUseUART = 0;
}

// end of file