interrupts.c

ucos on sa1200 from ixp1200 EB

        case I2O_INPOST:
            pciCsrWr((void *)(CSR_BASE + IRQ_ENABLE_SET),(unsigned int)I2O_INPOST_INT);
            break;

        case DISCARD_TIMER:
            pciCsrWr((void *)(CSR_BASE + IRQ_ENABLE_SET),(unsigned int)DISCARD_TIMER_INT);
            break;

        case DATA_PARITY:
            pciCsrWr((void *)(CSR_BASE + IRQ_ENABLE_SET),(unsigned int)DATA_PARITY_INT);
            break;

        case PCI_MASTER_ABORT:
            pciCsrWr((void *)(CSR_BASE + IRQ_ENABLE_SET),(unsigned int)PCI_MASTER_ABORT_INT);
            break;

        case PCI_TARGET_ABORT:
            pciCsrWr((void *)(CSR_BASE + IRQ_ENABLE_SET),(unsigned int)PCI_TARGET_ABORT_INT);
            break;

        case PCI_PARITY:
            pciCsrWr((void *)(CSR_BASE + IRQ_ENABLE_SET),(unsigned int)PCI_PARITY_INT);
            break;

        default:
            retval = SA_FAIL;
            break;
    }

    SAr_EnableInt(origIntMask);

    return(retval);
}


int SA_IRQ_Disable(IntSource intSource)
{
    int retval = SA_SUCCESS;

    unsigned int origIntMask = SAr_DisableInt();

    switch (intSource)
    {
        case MICRO_THREAD:
            *(unsigned int*)IREG = (*(unsigned int*)IREG & ~UEIRQ_ENABLE) & 0xF0000000;
            break;

        case EXTERNAL_C_PIN:
            *(unsigned int*)IREG = (*(unsigned int*)IREG & ~CINTIRQ_ENABLE) & 0xF0000000;
            break;

        case REAL_TIME_CLOCK:
			*(unsigned int*)RTC_DIV =
		        (*(unsigned int*)RTC_DIV & ~RTC_INT_ENABLE) | RTC_WRITE_ENABLE;
            break;

        case SERIAL:
            /* There are two interrupts, but we have only one entry here.
             * So we don't do enable/disable in this API
             */
            retval = SA_FAIL;
            break;

        case SRAM_MEMORY:
            *(unsigned int*)SRAM_CSR =
                (*(unsigned int*)SRAM_CSR & ~SRAM_IRQ) & 0xFFFFFFFC;
            break;

        case SDRAM_MEMORY:
            *(unsigned int*)SDRAM_CSR &= ~SDRAM_EN_IRQ;
            break;

        case PCI_DOORBELL:
            pciCsrWr((void *)(CSR_BASE + IRQ_ENABLE_CLEAR),(unsigned int)DOORBELL_INT);
            break;

        case SOFT:
            pciCsrWr((void *)(CSR_BASE + IRQ_ENABLE_CLEAR),(unsigned int)SOFT_INT);
            break;

        case TIMER1:
            pciCsrWr((void *)(CSR_BASE + IRQ_ENABLE_CLEAR),(unsigned int)TIMER1_INT);
            break;

        case TIMER2:
            pciCsrWr((void *)(CSR_BASE + IRQ_ENABLE_CLEAR),(unsigned int)TIMER2_INT);
            break;

        case TIMER3:
            pciCsrWr((void *)(CSR_BASE + IRQ_ENABLE_CLEAR),(unsigned int)TIMER3_INT);
            break;

        case TIMER4:
            pciCsrWr((void *)(CSR_BASE + IRQ_ENABLE_CLEAR),(unsigned int)TIMER4_INT);
            break;

        case DMA1:
            pciCsrWr((void *)(CSR_BASE + IRQ_ENABLE_CLEAR),(unsigned int)DMA1_INT);
            break;

        case DMA2:
            pciCsrWr((void *)(CSR_BASE + IRQ_ENABLE_CLEAR),(unsigned int)DMA2_INT);
            break;

        case PCI_IRQ_L:
            pciCsrWr((void *)(CSR_BASE + IRQ_ENABLE_CLEAR),(unsigned int)PCI_IRQ_L_INT);
            break;

        case DMA1_NOT_BUSY:
            pciCsrWr((void *)(CSR_BASE + IRQ_ENABLE_CLEAR),(unsigned int)DMA1_NOT_BUSY_INT);
            break;

        case DMA2_NOT_BUSY:
            pciCsrWr((void *)(CSR_BASE + IRQ_ENABLE_CLEAR),(unsigned int)DMA2_NOT_BUSY_INT);
            break;

        case START_BIST:
            pciCsrWr((void *)(CSR_BASE + IRQ_ENABLE_CLEAR),(unsigned int)START_BIST_INT);
            break;

        case SERR:
            pciCsrWr((void *)(CSR_BASE + IRQ_ENABLE_CLEAR),(unsigned int)SERR_INT);
            break;

        case SDRAM_PARITY:
            pciCsrWr((void *)(CSR_BASE + IRQ_ENABLE_CLEAR),(unsigned int)SDRAM_PARITY_INT);
            break;

        case I2O_INPOST:
            pciCsrWr((void *)(CSR_BASE + IRQ_ENABLE_CLEAR),(unsigned int)I2O_INPOST_INT);
            break;

        case DISCARD_TIMER:
            pciCsrWr((void *)(CSR_BASE + IRQ_ENABLE_CLEAR),(unsigned int)DISCARD_TIMER_INT);
            break;

        case DATA_PARITY:
            pciCsrWr((void *)(CSR_BASE + IRQ_ENABLE_CLEAR),(unsigned int)DATA_PARITY_INT);
            break;

        case PCI_MASTER_ABORT:
            pciCsrWr((void *)(CSR_BASE + IRQ_ENABLE_CLEAR),(unsigned int)PCI_MASTER_ABORT_INT);
            break;

        case PCI_TARGET_ABORT:
            pciCsrWr((void *)(CSR_BASE + IRQ_ENABLE_CLEAR),(unsigned int)PCI_TARGET_ABORT_INT);
            break;

        case PCI_PARITY:
            pciCsrWr((void *)(CSR_BASE + IRQ_ENABLE_CLEAR),(unsigned int)PCI_PARITY_INT);
            break;

        default:
            retval = SA_FAIL;
            break;
    }

    SAr_EnableInt(origIntMask);

    return(retval);
}


/*
**  void SA_IRQ_InitDoorBell()
**
**  DESCRIPTION
**      Initialize doorbell register.
**      Hook up an interrupt service routine to
**      doorbell register.
**      Enable doorbell interrupt.
** 
**  RETURNS
**      None.
*/
void SA_IRQ_InitDoorBell(PFVI intServiceRoutine)
{
    unsigned int origIntMask = SAr_DisableInt();

    SA_IRQ_Disable(PCI_DOORBELL);

    // Setup doorbell register's directions
    //
	pciCsrWr((void *)(CSR_BASE + DBELL_PCI_MASK),(unsigned int)0);
	pciCsrWr((void *)(CSR_BASE + DBELL_SA_MASK),(unsigned int)0xFFFFFFFF);

	pciCsrWr((void *)(CSR_BASE + DOORBELL_SETUP),(unsigned int)0xFFFFFFFF);

    SA_IRQ_Connect(PCI_DOORBELL, intServiceRoutine, 0);

    SA_IRQ_Enable(PCI_DOORBELL);


    SAr_EnableInt(origIntMask);
}


/*
**  void SA_IRQ_InitSoft()
**
**  DESCRIPTION
**      Hook up an interrupt service routine to
**      soft interrupt.
**      Enable soft interrupt.
** 
**  RETURNS
**      None.
*/
void SA_IRQ_InitSoft(PFVI intServiceRoutine)
{
    unsigned int origIntMask = SAr_DisableInt();

    SA_IRQ_Disable(SOFT);
    SA_IRQ_Connect(SOFT, intServiceRoutine, 0);
    SA_IRQ_Enable(SOFT);

    SAr_EnableInt(origIntMask);
}

/*
**  void SA_SysTimer(void)
**
**  DESCRIPTION
** 
**  RETURNS
**      None.
*/
void SA_SysTimer_ISR(int IGNOR)
{
    *(unsigned int*)(CSR_BASE + TIMER_3_CLEAR) = 0xFFFFFFFF;
    OSTimeTick();
}


/*
**  void SA_InitSysTimer(void)
**
**  DESCRIPTION
** 
**  RETURNS
**      None.
*/
void SA_InitSysTimer(void)
{
    unsigned int origIntMask = SAr_DisableInt();

    SA_IRQ_Disable(TIMER3);

#ifdef SA1200_A0
	 mSEC_1 = 100000000/1000;
#else
	if (0 == IXP1200_SysCpuRev)
	{ // set timing for 162mHz
	 mSEC_1 = 162200000/1000;
	}
	else
	{ // set timing for 200mHz
	 mSEC_1 = 199066000/1000;
	}
#endif

    mSEC_5		= (mSEC_1 * 5);
    mSEC_10		= (mSEC_1 * 10);
    mSEC_100    = (mSEC_1 * 100);
    SEC_1       = (mSEC_1 * 1000);
    SEC_10      = (SEC_1  * 10);
    OSTime = 0;
    /* Timer 3 used as an OS timer */
    *(unsigned int*)(CSR_BASE + TIMER_3_LOAD) = mSEC_10;

    /* Timer is periodic, and enabled */
    *(unsigned int*)(CSR_BASE + TIMER_3_CONTROL) = 0xC0;
    SA_IRQ_Connect(TIMER3, SA_SysTimer_ISR, 0);
    SA_IRQ_Enable(TIMER3);
    SAr_EnableInt(origIntMask);
}

// --------------------
// Fast Interrupt (FIQ)
// --------------------

IntHandler FIQ_Handlers[MAX_NUM_OF_SOURCES];

/*
**  void SA_InitFIQ()
**
**  DESCRIPTION
**      Disable FIQ.
**      Initialize FIQ stack and install a FIQ
**      interrupt vector.
** 
**  RETURNS
**      None.
*/
void SA_InitFIQ(void)
{
    int ii;

    unsigned int origIntMask = SAr_DisableInt();

    /* Initialize internal vector table */
    for (ii = 0; ii < MAX_NUM_OF_SOURCES; ii++)
    {
        FIQ_Handlers[ii].func = 0;
        FIQ_Handlers[ii].data = 0;
    }

    SAr_DisableAllFIQs();

    /* install FIQ Interrupt Service Routine */
    *(unsigned int*)FIQ_VECTOR = (unsigned int)SAir_FIQTrapWrap;

    SAr_EnableInt(origIntMask);
}


/*
**  void SA_FIQ_Connect()
**
**  DESCRIPTION
**      Register ISR for FIQ interrupts.
** 
**  RETURNS
**      success: original interrupt handler;
**      error: IntHandler.func == -1.
*/
IntHandler SA_FIQ_Connect(  IntSource intSource,
                            PFVI intServiceRoutine,
                            int userParam)
{
    IntHandler retval;

    unsigned int origIntMask = SAr_DisableInt();

    if ((intSource >= 0) &&
        (intSource < MAX_NUM_OF_SOURCES) &&
        (intSource != SERIAL) &&
		!((intSource == REAL_TIME_CLOCK) &&
            (*(unsigned int*)RTC_DIV & RTC_IRQ_SELECT)))
    {
        /* Return old interrupt handler */
        retval = FIQ_Handlers[intSource];
        /* install the new handler */
        FIQ_Handlers[intSource].func = intServiceRoutine;
        FIQ_Handlers[intSource].data = userParam;
    }
    else
        retval.func = (PFVI)-1;

    SAr_EnableInt(origIntMask);

    return(retval);
}


/*
**  void SA_FIQ_Dispatcher()
**
**  DESCRIPTION
**      Sort out different FIQ interrupts.
**      Read different interrupt sourse status registers
**      to determine what interrupt(s) we have and call
**      their ISR respectively.
** 
**  RETURNS
**      None.
*/
void SA_FIQ_Dispatcher(void)
{
    unsigned int FIQ_Status;
    unsigned int PCI_FIQ_Status;
    FIQ_Status = *(unsigned int*)(FIQ);

    // External C pin interrupt (MAC device interrupt)
    //
    if (FIQ_Status & F_CINT)
    {
        if (FIQ_Handlers[EXTERNAL_C_PIN].func)
            (FIQ_Handlers[EXTERNAL_C_PIN].func)(FIQ_Handlers[EXTERNAL_C_PIN].data);
        else
        {
            // Clear CINT interrupt, if driver is not there.
            *(unsigned int*)IREG |= CINT_BIT;
        }
    }

    // Micro engin/thread interrupt
    //
    if (FIQ_Status & F_UENG)
    {
        if (FIQ_Handlers[MICRO_THREAD].func)
            (FIQ_Handlers[MICRO_THREAD].func)(FIQ_Handlers[MICRO_THREAD].data);
        else
        {
            // Clear UENG interrupt, if driver is not there.
            *(unsigned int*)IREG &= 0xF8000000;
        }
    }

    // Real Time Clock Interrupt
    //
    if (FIQ_Status & F_RTC)
    {
        if (FIQ_Handlers[REAL_TIME_CLOCK].func)
            (FIQ_Handlers[REAL_TIME_CLOCK].func)(FIQ_Handlers[REAL_TIME_CLOCK].data);
    }

    // SRAM Interrupt
    //
    if (FIQ_Status & F_SRAM)
    {
        if (FIQ_Handlers[SRAM_MEMORY].func)
            (FIQ_Handlers[SRAM_MEMORY].func)(FIQ_Handlers[SRAM_MEMORY].data);
        else
            *(unsigned int*)SRAM_CSR &= ~(SRAM_RLRS | SRAM_RLS);
    }

    // SRAM Interrupt
    //
    if (FIQ_Status & F_SDRAM)
    {
        if (FIQ_Handlers[SDRAM_MEMORY].func)
            (FIQ_Handlers[SDRAM_MEMORY].func)(FIQ_Handlers[SDRAM_MEMORY].data);
    }

    // Interrupts generated by PCI unit
    //
    if (FIQ_Status & F_PCI)
    {
        PCI_FIQ_Status = *(unsigned int*)(CSR_BASE + FIQ_STATUS);

        if (PCI_FIQ_Status & DOORBELL_INT)
        {
            if (FIQ_Handlers[PCI_DOORBELL].func)
                (FIQ_Handlers[PCI_DOORBELL].func)(FIQ_Handlers[PCI_DOORBELL].data);
        }

        if (PCI_FIQ_Status & SOFT_INT)
        {
            if (FIQ_Handlers[SOFT].func)
                (FIQ_Handlers[SOFT].func)(FIQ_Handlers[SOFT].data);
			else
				pciCsrWr((void *)(CSR_BASE + FIQ_SOFT),(unsigned int)0);
        }

        if (PCI_FIQ_Status & TIMER1_INT)
        {
            if (FIQ_Handlers[TIMER1].func)
                (FIQ_Handlers[TIMER1].func)(FIQ_Handlers[TIMER1].data);
			else
				*(unsigned int*)(CSR_BASE + TIMER_1_CLEAR) = 0xFFFFFFFF;
        }

        if (PCI_FIQ_Status & TIMER2_INT)
        {
            if (FIQ_Handlers[TIMER2].func)
                (FIQ_Handlers[TIMER2].func)(FIQ_Handlers[TIMER2].data);
			else
				*(unsigned int*)(CSR_BASE + TIMER_2_CLEAR) = 0xFFFFFFFF;
        }

        if (PCI_FIQ_Status & TIMER3_INT)
        {
            if (FIQ_Handlers[TIMER3].func)
                (FIQ_Handlers[TIMER3].func)(FIQ_Handlers[TIMER3].data);
			else
				*(unsigned int*)(CSR_BASE + TIMER_3_CLEAR) = 0xFFFFFFFF;
        }

        if (PCI_FIQ_Status & TIMER4_INT)
        {
            if (FIQ_Handlers[TIMER4].func)
                (FIQ_Handlers[TIMER4].func)(FIQ_Handlers[TIMER4].data);