spi.h

MANTIS是由科罗拉多大学开发的传感器网络嵌入式操作系统。 这是mantis的0.9.5版本的源码。

//  This file is part of MANTIS OS, Operating System
//  See http://mantis.cs.colorado.edu/
//
//  Copyright (C) 2003,2004,2005 University of Colorado, Boulder
//
//  This program is free software; you can redistribute it and/or
//  modify it under the terms of the mos license (see file LICENSE)

#ifndef __SPI_H__
#define __SPI_H__

/** @file spi.h
 * @brief SPI Driver for all platforms.
 */

/* SPI Macros for the TELOSB Platform
 *
 *
 *
 */
#ifdef PLATFORM_TELOSB

#define SPI_WAIT_EOTX() while(!(U0TCTL & TXEPT))
#define SPI_WAIT_EORX() while(!(IFG1 & URXIFG0))

#define SPI_TX_BUF U0TXBUF
#define SPI_RX_BUF U0RXBUF

// little hack :)
#define EIMSK P1IE

// initialize UART to SPI Mode, setup Pins
#define PLAT_SPI_INIT() do {				\
      U0CTL = SWRST;					\
      /* 8 bits, SPI, Master, Reset State */		\
      U0CTL |= CHAR | SYNC | MM;			\
      /* Delay Tx Half Cycle, SMCLK, 3 Pin Mode */	\
      U0TCTL = CKPH | SSEL_3 | STC | TXEPT;		\
      /* Baud Rate & Modulation Control Not Used */	\
      U0BR0  = 0x02;					\
      U0BR1  = 0x00;					\
      U0MCTL = 0x00;					\
      /* make sure Uart0 interrupts are off */		\
      IE1 &= ~(UTXIE0 | URXIE0);			\
      /* set peripheral mode for MOSI MISO UCLK */	\
      MASK_3(P3SEL, 1, 2, 3);				\
      /*UNMASK_1(P4SEL, CC2420_SFD_PIN);*/		\
      /* enable UART0 SPI, send, recv */		\
      ME1 |= USPIE0 /*| UTXE0 | URXE0*/;		\
      /* Disable Reset State */				\
      U0CTL &= ~SWRST;					\
   } while(0)

// enable Port 1, Pin 0 (FIFOP) Interrupt
#define PLAT_ENABLE_FIFOP_INT() do {		\
      P1DIR |=  (1 << 0);			\
      P1IES &= ~(1 << 0);			\
      P1IE  |=  (1 << 0);			\
   } while(0)


/* SPI Macros the AVR Arch
 *
 *
 *
 */

#elif defined(ARCH_AVR)

// other
#define SPI_WAIT() { while (!(SPSR & (1 << SPIF))); }
#define SPI_WAIT_EOTX() SPI_WAIT()
#define SPI_WAIT_EORX() SPI_WAIT()

#define SPI_TX_BUF SPDR
#define SPI_RX_BUF SPDR


#define PLAT_SPI_INIT() do {			\
      MASK_2(SPCR, SPE, MSTR);			\
      MASK_1(SPSR, SPI2X);			\
   } while(0)

#define PLAT_ENABLE_FIFOP_INT() do {			\
      EICRB |= (0x3 << (CC2420_FIFOP_PIN - 4) * 2);	\
      MASK_1(EIFR, CC2420_FIFOP_PIN);			\
   } while(0)

#endif

static inline void spi_tx_byte(uint8_t byte)
{
   SPI_TX_BUF = byte;
   SPI_WAIT_EOTX();
}

static inline uint8_t spi_rx(void)
{
   SPI_TX_BUF = 0;
   SPI_WAIT_EOTX();
   SPI_WAIT_EORX();
   return SPI_RX_BUF;
}

static inline void spi_rx_garbage(void)
{
   SPI_TX_BUF = 0;
   SPI_WAIT_EOTX();
   SPI_WAIT_EORX();
   uint8_t trash = SPI_RX_BUF;
}

// check
static inline uint16_t spi_rx_word(void)
{
   uint16_t ret = 0;
   SPI_TX_BUF = 0;
   SPI_WAIT_EOTX();
   SPI_WAIT_EORX();
   ret = SPI_RX_BUF << 8;
   SPI_TX_BUF = 0;
   SPI_WAIT_EOTX();
   SPI_WAIT_EORX();
 
   ret |= SPI_RX_BUF;
   
   return ret;
}




#endif