pre_proc.asm

TI C54写的G729代码,视线8kbps高质量语音编码,汇编优化

        .mmregs

        .include  ..\include\const.h

        .data
stt     .word    0x3

        .text
        .def    Pre_Process
        .def    L_Shl

        .ref    ptr_pre_hpf_u    ; ld8k.mem
        .ref    b140_Q12         ; tab_ld8k.asm
        .ref    a140_Q12         ; tab_ld8k.asm

;------------------------------------------------------------------------
; 2nd order high pass filter with cut off frequency at 140 Hz.
; Designed with SPPACK efi command -40 dB att, 0.25 ri.
;
; Algorithm:
;
;  y[i] = b[0]*x[i]/2 + b[1]*x[i-1]/2 + b[2]*x[i-2]/2
;                     + a[1]*y[i-1]   + a[2]*y[i-2];
;
;     b[3] = {0.92727435E+00, -0.18544941E+01, 0.92727435E+00};
;     a[3] = {0.10000000E+01, 0.19059465E+01, -0.91140240E+00};
;
;  Input are divided by two in the filtering process.
;-----------------------------------------------------------------------
;
;  y(n)  = b[0]*x(n)/2 + u1(n-1)
;  u1(n) = b[1]*x(n)/2 + a[1]*y(n) + u2(n-1)
;  u2(n) = b[2]*x(n)/2 + a[2]*y(n)
;-----------------------------------------------------------------------
;  Input Registers : BRC = Lg
;                    AR3 -> signal[]
;                    BK = L_TOTAL
;
;  Modified Registers : BRC
;                       A, B
;                       AR1, AR2, AR3, AR4, AR5
;-----------------------------------------------------------------------

        .asg    "AR1", pU140Q28
        .asg    "AR2", pY140
        .asg    "AR3", pSignal
        .asg    "AR4", pB140Q12
        .asg    "AR5", pA140Q12
        .text
Pre_Process:

        STM     #b140_Q12, pB140Q12               ; pB140Q12 -> b0
        STM     #a140_Q12 + 1, pA140Q12           ; pA140Q12 -> a1
        MVDM    ptr_pre_hpf_u, pU140Q28           ; pU140Q28 -> u1_hi

        RPTBD   #HPF140 - 1
        STM     #BL, pY140                        ; pY140 -> BL

                DLD     *pU140Q28+, B             ; pU140Q28 -> u2_hi
                MAC     *pSignal, *pB140Q12+, B   ; B = y(n), pB140Q12 -> b1

                STM     #BL, AR6             ; clear lsb bits
                ANDM    #0fffeh, *AR6        ; Masking
                CALL    L_Shl                ; Shift three

                LD      #0, A
                MACSU   *pY140+, *pA140Q12, A
                SFTA    A, -16
                MAC     *pY140-, *pA140Q12+, A    ; A = y(n) * a1
                                                  ; pA140Q12 -> a2

                STM     #AL, AR6                  ; clear lsb to prevent acc error
                ANDM     #0fffeh, *AR6            ; Masking



                DADD    *pU140Q28-, A             ; A = a1 * y(n) + u2(n-1)
                                                  ; pU140Q28 -> u1_hi
                MAC     *pSignal, *pB140Q12-, A   ; A = u1(n), pB140Q12 -> b0 = b2
                DST     A, *pU140Q28+             ; update u1, pU140Q28 -> u2_hi

                LD       #0, A
                MACSU    *pY140+, *pA140Q12, A
                SFTA     A, -16
                MAC      *pY140-, *pA140Q12-, A   ; A = a2 * y(n)
                                                  ; pA140Q12 -> a1

                STM     #AL, AR6                  ; clear lsb to prevent acc error
                ANDM     #0fffeh, *AR6


                MAC     *pSignal, *pB140Q12, A    ; A = u2(n)
                DST     A, *pU140Q28-             ; update u2, pU140Q28 -> u1_hi

                ADD     #1, 15, B                 ; add 0x8000 to round
                STL     B, -16, *pSignal+     ; update signal, pSignal -> x(n+1)
HPF140:
				RET              

L_Shl:
         STM       #stt, AR6
         ST        #3 , *AR6
$1:
         LD        #16383, 16, A    ; set 0x3fff to a msb 16 bits
         OR        #65535, A, A     ; set A to 0x3fffffff
         SUB       B, A             ; var1 - 0x3FFFFFFF 
         BC        $2,AGEQ          ; var1 > 0x3FFFFFFF then 
         ; branch occurs

         LD        #32767, 16, B    ; set max 0x7FFFFFFF to return value
         RET;
         ; branch occurs

$2:      ; here no overflow
         LD        #-16384, 16, A   ; 0xc0000000 to A
         SUB       B, A             ; check var1 < 0xc0000000
         BC        $3, ALEQ        ; if var1 < 0xc0000000 then overflow
         ; branch occurs

         LD        #32768, 16, B    ; var1 < 0xc0000000, set 0x80000000 to A
         RET;

$3:   
         SFTA      B, #1, B         ; A * 2 -> A
         ADDM      #-1, *AR6        ; var2 - 1 -> var2
         LD        *AR6, A          ; var2 -> A
         BC        $1, AGT          ; var2 > 0, then once more, otherwise return
         ; branch occurs
         RET;