xspclk.vhd

用VHDL语言编写的代码

--------------------------------------------------------------------------------
-- Copyright (c) 2000 by Trenz Electronic.
-- Duenner Kirchweg 77, 32257 Buende, Germany, www.trenz-electronic.de
--     
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--     
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--     
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
--------------------------------------------------------------------------------
-- Project:      Full-Speed USB 1.1 Function Controller
-- File:         xspCLK.vhd
-- Description:  XSP-010 board, Clock divider and reset.
-- Version:      FB, 2000jul29
--------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity xspCLK is
	port(
		clk:  in  STD_LOGIC; -- 48MHz clock
		rst:  in  STD_LOGIC; -- async reset
		clko: out STD_LOGIC; -- 24MHz clock
		rsto: out STD_LOGIC  -- 8051 reset
		);
end xspCLK;

--------------------------------------------------------------------------------
architecture BHV of xspCLK is
	signal div: STD_LOGIC;
begin
	clko<= div;
	rsto<= rst;
	
	process(clk, rst)
	begin
		if rst= '1' then
			div<= '0';
		elsif rising_edge(clk) then
			div<= not(div);
		end if;
	end process;
	
end BHV;

--------------------------------------------------------------------------------
-- end of file