main.asm

ADSP与NANDFLASH的连接

/******************************************************************************/
//
// Name: 	NAND FLASH interface with ADSP-21262
//
/******************************************************************************

(C) Copyright 2005 - Analog Devices, Inc.  All rights reserved.

File Name:		main.asm

Date Modified:	31/08/05 - AV	-	Rev 1.0

Software:       VisualDSP++4.0

Purpose:		Program to demonstrate Flash memory interface on paralle port
				
*******************************************************************************/

#include <def21262.h>
//External function delcaration
.extern FLASH_BLOCK_Erase_Command;
.extern FLASH_READ_Command;
.extern FLASH_PROGRAM_Command;
.extern InitSRU;
//##########################################################################

//Global declarations
.global block_erase_cmds;
.global page_read_cmd;
.global page_program_cmds;
.global read_status_cmd;
//##########################################################################

.section/pm seg_rth;
	nop;nop;nop;nop;nop;jump start;
	
.section/pm seg_ppi_int;
	jump ppi_intr;rti;rti;rti;

.section/pm seg_dail_int;
	jump dail_int_flash_ready;rti;rti;rti;
	
	
.section/dm seg_dmda;
	.var pageREAD[528]; //data read from FLASH will be stored here
	.var pageWRITE[528];//data to program FLASH memory is initialized here
	
	//Init Flash commands in memory
	.var block_erase_cmds[2] = 	{0x60,0xd0};
	.var page_program_cmds[2] = {0x80,0x10};
	.var page_read_cmd[1] =		{0x00}; 
	.var read_status_cmd[1] =   {0x70};
		
.section/pm seg_pmco;
start:
		
	//Setting up FLAGs to control CE#, CLE and ALE of the FLASH
	bit set FLAGS FLG0O | FLG1O | FLG2O;//FLAGs configured as outputs
	bit set FLAGS FLG0;//FLAG0 drives CE# of FLASH
	bit clr FLAGS FLG1;//FLAG1 drives CLE of FLASH
	bit clr FLAGS FLG2;//FLAG2 drives ALE of FLASH
	
	//Connect DAI pin1 to DAI Interrupt
	CALL InitSRU; //DAI pin 20 is connnected to MISCA0
	CALL IntSetUp;//Interrupts required are set-up here
	CALL InitData;//Initialize data to be written to FLASH in to DSP's internal memory
		
	
	//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
	//FLASH should be erased "All 0xFF" before programing
	/* Before calling block erase function, R13, R14 and R15 should be initialized with
	   the address of block that needs to be erased.
	   R13 <- row0 address
	   R14 <- row1 address
	   R15 <- row2 address
	*/
	//parameter passing for block erase fucntion
	r13 = 0xE0; r14 = 0x1; r15 = 0x1;
	CALL FLASH_BLOCK_Erase_Command;
	//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
	
	
	
	//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
	/* Before calling flash program function, R12, R13, R14 and R15 should be initialized with
	   the address of column and rows
	   R12 <- column address
	   R13 <- row0 address
	   R14 <- row1 address
	   R15 <- row2 address
	*/
	//parameter passing for program page command
	r12 = 0x0; r13 = 0xE0; r14 = 0x1; r15 = 0x1;
	//Set-up the pointer to internal memory
	i4 = pageWRITE;//buffer points to internal memory - data to WRITE/PROGRAM is picked up from here
	CALL FLASH_PROGRAM_Command;
	//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
	
	
	
	//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
	/* Before calling flash read function, R12, R13, R14 and R15 should be initialized with
	   the address of column and rows
	   R12 <- column address
	   R13 <- row0 address
	   R14 <- row1 address
	   R15 <- row2 address
	*/
	//parameter passing for read page command
	r12 = 0x0; r13 = 0xE0; r14 = 0x1; r15 = 0x1;
	//Set-up the pointer to internal memory
	i4 = pageREAD;//buffer points to internal memory - READ data from FLASH is stored here
	CALL FLASH_READ_Command;
	//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

	jump (pc,0);



	

/*	BUSY# signal from FLASH is connected to DAI Interrupt signal DAI1
	When device is BUSY, the signal goes LO and once the device is ready/OR done
	with transaction, the BUSY# signal goes HI. This triggers DAI Interrupt.
	Therefore, whenever BUSY# condition needs to be checked, "idle;" instruction is
	inserted in the code.

*/

//Parallel port Interrupt Service Routine
ppi_intr:
	nop;nop;
	rti;
//##########################################################################
	
//DAI Interrupt Service Routine
dail_int_flash_ready:
	ustat1 = dm(DAI_IRPTL_L);//This should clear the DAI interrupt
	nop;nop;
	rti;
//##########################################################################

//Interrupts set-up sub-routine
IntSetUp:
	//Set up DAI Interrupt here
	ustat1 = dm(DAI_IRPTL_RE);
	bit set ustat1 SRU_EXTMISCA0_INT;
	dm(DAI_IRPTL_RE) = ustat1;
	
	//Enable DAI and PP Interrupts 
	bit set LIRPTL DAILIMSK;
	bit set LIRPTL PPIMSK;
	bit set MODE1 IRPTEN;//Global Interrupt enable

	//Some delay
	lcntr = 0x100; do wait_while until lce;
	wait_while: nop;
	RTS;
//##########################################################################


//Data Initialization sub-routine - Initializes data in to internal memory of processor
InitData:
	//Init pageWRITE data in internal memory
	i2 = pageWRITE;
	m2 = 1;
	r2 = 0;
	
	lcntr = 528, do pageWRITE_init until lce;
	dm(i2,m2) = r2;
	r2 = r2+1;
	pageWRITE_init: nop;	
	//Initialization of data in internal memory OVER	
	RTS;
//##########################################################################