design_spec.dc

来自「DMA的控制器的IP核,和ATA控制器配合,可以实现DMA方式高速传输数据.」· DC 代码 · 共 27 行

#################################################################################
#
# Design Specification
#
# Author: Rudolf Usselmann
#         [e-mail]
#
# Revision:
# 3/7/01 RU Initial Sript
#
#
#################################################################################

# ==============================================
# Setup Design Parameters

set design_files {wb_dma_inc30r wb_dma_ch_arb wb_dma_pri_enc_sub wb_dma_ch_pri_enc wb_dma_ch_sel wb_dma_ch_rf wb_dma_rf wb_dma_wb_mast wb_dma_wb_slv  wb_dma_wb_if wb_dma_de wb_dma_top }

set design_name wb_dma_top
set active_design wb_dma_top
 
# Next Statement defines all clocks and resets in the design
set special_net {rst clk}
 
set hdl_src_dir ../../rtl/verilog/