tests.v

DMA的控制器的IP核,和ATA控制器配合,可以实现DMA方式高速传输数据.

	if( (s1.mem[n+0] !== d0) | (s1.mem[n+1] !== d1) |
		(s1.mem[n+2] !== d2) | (s1.mem[n+3] !== d3) )
	   begin
		$display("ERROR: Memory Read Data (%0d) Mismatch: (%0t)",n,$time);
		$display("D0: Expected: %x, Got %x", s1.mem[n+0], d0);
		$display("D1: Expected: %x, Got %x", s1.mem[n+1], d1);
		$display("D2: Expected: %x, Got %x", s1.mem[n+2], d2);
		$display("D3: Expected: %x, Got %x", s1.mem[n+3], d3);
		error_cnt = error_cnt + 1;
	   end
      end
 end


$display("\nINFO: PT10 RD1");
   for(n=0;n<512;n=n+1)
     begin
	m0.wb_rd1(n<<2,4'hf,d0);

	if( s1.mem[n] !== d0 )
	   begin
		$display("ERROR: Memory Read Data (%0d) Mismatch: (%0t)",n,$time);
		$display("D0: Expected: %x, Got %x", s1.mem[n], d0);
		error_cnt = error_cnt + 1;
	   end
      end


show_errors;
$display("*****************************************************");
$display("*** Test DONE ...                                 ***");
$display("*****************************************************\n");
end
endtask


task pt01_rd;

// Misc Variables
reg	[31:0]	d0,d1,d2,d3;
integer		d,n;

begin
$display("\n");
$display("*****************************************************");
$display("*** Running Path Through 0->1 Read Test ....      ***");
$display("*****************************************************\n");

s0.fill_mem(1);
s1.fill_mem(1);

d=1;
n=0;
for(d=0;d<16;d=d+1)
 begin
   $display("INFO: PT01 RD4, delay %0d",d);
   for(n=0;n<512;n=n+4)
     begin
	m1.wb_rd4(n<<2,4'hf,d,d0,d1,d2,d3);
	@(posedge clk);

	if( (s0.mem[n+0] !== d0) | (s0.mem[n+1] !== d1) |
		(s0.mem[n+2] !== d2) | (s0.mem[n+3] !== d3) )
	   begin
		$display("ERROR: Memory Read Data (%0d) Mismatch: (%0t)",n,$time);
		$display("D0: Expected: %x, Got %x", s0.mem[n+0], d0);
		$display("D1: Expected: %x, Got %x", s0.mem[n+1], d1);
		$display("D2: Expected: %x, Got %x", s0.mem[n+2], d2);
		$display("D3: Expected: %x, Got %x", s0.mem[n+3], d3);
		error_cnt = error_cnt + 1;
	   end
      end
 end

$display("\nINFO: PT01 RD1");
   for(n=0;n<512;n=n+1)
     begin
	m1.wb_rd1(n<<2,4'hf,d0);

	if( s0.mem[n+0] !== d0 )
	   begin
		$display("ERROR: Memory Read Data (%0d) Mismatch: (%0t)",n,$time);
		$display("D0: Expected: %x, Got %x", s0.mem[n+0], d0);
		error_cnt = error_cnt + 1;
	   end
      end

show_errors;
$display("*****************************************************");
$display("*** Test DONE ...                                 ***");
$display("*****************************************************\n");
end
endtask




task pt10_wr;

// Misc Variables
reg	[31:0]	d0,d1,d2,d3;
integer		d,n;

begin

$display("\n");
$display("*****************************************************");
$display("*** Running Path Through 1->0 Write Test ....     ***");
$display("*****************************************************\n");


s0.fill_mem(1);
s1.fill_mem(1);
d=1;
n=0;
for(d=0;d<16;d=d+1)
 begin
   $display("INFO: PT10 WR4, delay %0d",d);
   for(n=0;n<512;n=n+4)
     begin

	d0 = $random;
	d1 = $random;
	d2 = $random;
	d3 = $random;
	m0.wb_wr4(n<<2,4'hf,d,d0,d1,d2,d3);
	@(posedge clk);

	if( (s1.mem[n+0] !== d0) | (s1.mem[n+1] !== d1) |
		(s1.mem[n+2] !== d2) | (s1.mem[n+3] !== d3) )
	   begin
		$display("ERROR: Memory Write Data (%0d) Mismatch: (%0t)",n,$time);
		$display("D0: Expected: %x, Got %x", s1.mem[n+0], d0);
		$display("D1: Expected: %x, Got %x", s1.mem[n+1], d1);
		$display("D2: Expected: %x, Got %x", s1.mem[n+2], d2);
		$display("D3: Expected: %x, Got %x", s1.mem[n+3], d3);
		error_cnt = error_cnt + 1;
	   end
      end
 end

$display("\nINFO: PT10 WR1");
   for(n=0;n<512;n=n+1)
     begin
	d0 = $random;
	m0.wb_wr1(n<<2,4'hf,d0);
	@(posedge clk);

	if( s1.mem[n+0] !== d0 )
	   begin
		$display("ERROR: Memory Write Data (%0d) Mismatch: (%0t)",n,$time);
		$display("D0: Expected: %x, Got %x", s1.mem[n+0], d0);
		error_cnt = error_cnt + 1;
	   end
      end

show_errors;
$display("*****************************************************");
$display("*** Test DONE ...                                 ***");
$display("*****************************************************\n");
end
endtask



task pt01_wr;

// Misc Variables
reg	[31:0]	d0,d1,d2,d3;
integer		d,n;

begin

$display("\n");
$display("*****************************************************");
$display("*** Running Path Through 0->1 Write Test ....     ***");
$display("*****************************************************\n");


s0.fill_mem(1);
s1.fill_mem(1);

d=1;
n=0;
for(d=0;d<16;d=d+1)
 begin
   $display("INFO: PT01 WR4, delay %0d",d);
   for(n=0;n<512;n=n+4)
     begin

	d0 = $random;
	d1 = $random;
	d2 = $random;
	d3 = $random;
	m1.wb_wr4(n<<2,4'hf,d,d0,d1,d2,d3);
	@(posedge clk);

	if( (s0.mem[n+0] !== d0) | (s0.mem[n+1] !== d1) |
		(s0.mem[n+2] !== d2) | (s0.mem[n+3] !== d3) )
	   begin
		$display("ERROR: Memory Write Data (%0d) Mismatch: (%0t)",n,$time);
		$display("D0: Expected: %x, Got %x", s0.mem[n+0], d0);
		$display("D1: Expected: %x, Got %x", s0.mem[n+1], d1);
		$display("D2: Expected: %x, Got %x", s0.mem[n+2], d2);
		$display("D3: Expected: %x, Got %x", s0.mem[n+3], d3);
		error_cnt = error_cnt + 1;
	   end
      end
 end

   $display("\nINFO: PT01 WR1");
   for(n=0;n<512;n=n+1)
     begin
	d0 = $random;
	m1.wb_wr1(n<<2,4'hf,d0);
	@(posedge clk);

	if( s0.mem[n+0] !== d0 )
	   begin
		$display("ERROR: Memory Write Data (%0d) Mismatch: (%0t)",n,$time);
		$display("D0: Expected: %x, Got %x", s0.mem[n+0], d0);
		error_cnt = error_cnt + 1;
	   end
      end

show_errors;
$display("*****************************************************");
$display("*** Test DONE ...                                 ***");
$display("*****************************************************\n");
end
endtask







task show_errors;

begin

$display("\n");
$display("     +--------------------+");
$display("     |  Total ERRORS: %0d   |", error_cnt);
$display("     +--------------------+");

end
endtask



task hw_dma4;
input		quick;

integer		quick, tot_sz_max, chunk_sz_max, del_max;

reg	[7:0]	mode;
reg	[15:0]	chunk_sz, tot_sz;
integer		i, n,m0, m1, m2, m3, k,rep,del;
reg	[31:0]	int_src, d0,d1;
reg		do_rest;
integer		rest_del;
integer		rest_del_t;

begin
$display("\n\n");
$display("*****************************************************");
$display("*** HW DMA No Buffer Ext Descr. REST Test ...     ***");
$display("*****************************************************\n");

case(quick)
	default:
	   begin
		del_max = 6;
		tot_sz_max = 200;
		chunk_sz_max = 8;
	   end
	 1:
	   begin
		del_max = 4;
		tot_sz_max = 128;
		chunk_sz_max = 4;
	   end
	 2:
	   begin
		del_max = 3;
		tot_sz_max = 32;
		chunk_sz_max = 4;
	   end
endcase

mode = 1;
tot_sz = 32;
chunk_sz=7;
del = 0;
do_rest = 1;
rest_del = 7;

	m0.wb_wr1(`REG_BASE + `CH0_CSR,4'hf, 32'h0);
	m0.wb_wr1(`REG_BASE + `CH1_CSR,4'hf, 32'h0);
	m0.wb_wr1(`REG_BASE + `CH2_CSR,4'hf, 32'h0);
	m0.wb_wr1(`REG_BASE + `CH3_CSR,4'hf, 32'h0);

	m0.wb_rd1(`REG_BASE + `INT_SRCA, 4'hf, int_src);

for(tot_sz=1;tot_sz<tot_sz_max;tot_sz=tot_sz+1)
begin

if(tot_sz>4)	tot_sz = tot_sz + 4;
if(tot_sz>16)	tot_sz = tot_sz + 12;
if(tot_sz>64)	tot_sz = tot_sz + 48;

for(del=0;del<del_max;del=del+1)
//for(mode=0;mode<4;mode=mode+1)
//for(chunk_sz=0;chunk_sz<chunk_sz_max;chunk_sz=chunk_sz+1)

for(rest_del=0;rest_del<16;rest_del=rest_del + 1)
for(chunk_sz=1;chunk_sz<chunk_sz_max;chunk_sz=chunk_sz+1)
begin
do_rest = 1;
	s0.delay = del;
	s1.delay = del;

	s0.fill_mem(1);
	s1.fill_mem(1);

	s0.mem[0] = (32'h000c_0000 | (mode[1:0]<<16)) + tot_sz;
	s0.mem[1] = 32'h0000_0100;
	s0.mem[2] = 32'h0000_0900;
	s0.mem[3] = 32'h0000_0010;

	s0.mem[4] = (32'h001c_0000 | (mode[1:0]<<16)) + tot_sz;
	s0.mem[5] = 32'h0000_0100 + (tot_sz * 4);
	s0.mem[6] = 32'h0000_0900 + (tot_sz * 4);
	s0.mem[7] = 32'h0000_0000;

	s0.mem[8] = (32'h000c_0000 | (mode[1:0]<<16)) + tot_sz;
	s0.mem[9] = 32'h0000_1100;
	s0.mem[10] = 32'h0000_1900;
	s0.mem[11] = 32'h0000_0030;

	s0.mem[12] = (32'h001c_0000 | (mode[1:0]<<16)) + tot_sz;
	s0.mem[13] = 32'h0000_1100 + (tot_sz * 4);
	s0.mem[14] = 32'h0000_1900 + (tot_sz * 4);
	s0.mem[15] = 32'h0000_0000;

	s0.mem[16] = (32'h000c_0000 | (mode[1:0]<<16)) + tot_sz;
	s0.mem[17] = 32'h0000_2100;
	s0.mem[18] = 32'h0000_2900;
	s0.mem[19] = 32'h0000_0050;

	s0.mem[20] = (32'h001c_0000 | (mode[1:0]<<16)) + tot_sz;
	s0.mem[21] = 32'h0000_2100 + (tot_sz * 4);
	s0.mem[22] = 32'h0000_2900 + (tot_sz * 4);
	s0.mem[23] = 32'h0000_0000;

	s0.mem[24] = (32'h000c_0000 | (mode[1:0]<<16)) + tot_sz;
	s0.mem[25] = 32'h0000_3100;
	s0.mem[26] = 32'h0000_3900;
	s0.mem[27] = 32'h0000_0070;

	s0.mem[28] = (32'h001c_0000 | (mode[1:0]<<16)) + tot_sz;
	s0.mem[29] = 32'h0000_3100 + (tot_sz * 4);
	s0.mem[30] = 32'h0000_3900 + (tot_sz * 4);
	s0.mem[31] = 32'h0000_0000;

	m0.wb_wr1(`REG_BASE + `INT_MASKA,4'hf,32'hffff_ffff);

	m0.wb_wr1(`REG_BASE + `PTR0, 4'hf, 32'h0000_0000);
	m0.wb_wr1(`REG_BASE + `CH0_TXSZ,4'hf, {chunk_sz, 16'h0fff});
	m0.wb_wr1(`REG_BASE + `CH0_ADR0,4'hf,32'h0000_ffff);
	m0.wb_wr1(`REG_BASE + `CH0_ADR1,4'hf,32'h0000_ffff);

	m0.wb_wr1(`REG_BASE + `CH0_CSR,4'hf,
			//{25'h0000001, 4'b0111, 2'b00, 1'b1});
			{12'h0000, 3'b010, 1'b1, 9'h001, 4'b0111, 2'b00, 1'b1});

	m0.wb_wr1(`REG_BASE + `PTR1, 4'hf, 32'h0000_0020);
	m0.wb_wr1(`REG_BASE + `CH1_TXSZ,4'hf, {chunk_sz, 16'h0fff});
	m0.wb_wr1(`REG_BASE + `CH1_ADR0,4'hf,32'h0000_ffff);
	m0.wb_wr1(`REG_BASE + `CH1_ADR1,4'hf,32'h0000_ffff);

	m0.wb_wr1(`REG_BASE + `CH1_CSR,4'hf,
			//{25'h0000001, 4'b0111, 2'b00, 1'b1});
			{12'h0000, 3'b010, 1'b1, 9'h001, 4'b0111, 2'b00, 1'b1});

	m0.wb_wr1(`REG_BASE + `PTR2, 4'hf, 32'h0000_0040);
	m0.wb_wr1(`REG_BASE + `CH2_TXSZ,4'hf, {chunk_sz, 16'h0fff});
	m0.wb_wr1(`REG_BASE + `CH2_ADR0,4'hf,32'h0000_ffff);
	m0.wb_wr1(`REG_BASE + `CH2_ADR1,4'hf,32'h0000_ffff);

	m0.wb_wr1(`REG_BASE + `CH2_CSR,4'hf,
			//{25'h0000001, 4'b0111, 2'b00, 1'b1});
			{12'h0000, 3'b010, 1'b1, 9'h001, 4'b0111, 2'b00, 1'b1});

	m0.wb_wr1(`REG_BASE + `PTR3, 4'hf, 32'h0000_0060);
	m0.wb_wr1(`REG_BASE + `CH3_TXSZ,4'hf, {chunk_sz, 16'h0fff});
	m0.wb_wr1(`REG_BASE + `CH3_ADR0,4'hf,32'h0000_ffff);
	m0.wb_wr1(`REG_BASE + `CH3_ADR1,4'hf,32'h0000_ffff);

	m0.wb_wr1(`REG_BASE + `CH3_CSR,4'hf,
			//{25'h0000001, 4'b0111, 2'b00, 1'b1});
			{12'h0000, 3'b010, 1'b1, 9'h001, 4'b0111, 2'b00, 1'b1});


	ack_cnt_clr = 1;
	@(posedge clk);
	ack_cnt_clr = 0;

	if(chunk_sz==0)		k = 1;
	else
	   begin
		k = tot_sz/chunk_sz;
		if((k*chunk_sz) != tot_sz)	k = k + 1;
	   end

//$display("rest_del: %0d, k: %0d", rest_del, k);

	if(rest_del >= k)	rest_del_t = k - 1;
	else			rest_del_t = rest_del;

	k = k * 2;


	$write("Total Size: %0d, Delay: %0d REST_del: %0d ",tot_sz, del, rest_del_t);
	case(mode)
	   0: $display("Mode: 0->0, chunk_size: %0d", chunk_sz);
	   1: $display("Mode: 0->1, chunk_size: %0d", chunk_sz);
	   2: $display("Mode: 1->0, chunk_size: %0d", chunk_sz);
	   3: $display("Mode: 1->1, chunk_size: %0d", chunk_sz);
	endcase



//$display("k=%0d",k);

	fork
	   begin	// Hardware Handshake Channel 0
		repeat(5)	@(posedge clk);
		for(m0=0;m0 < k;m0=m0+1)
		   begin
			repeat(del)	@(posedge clk);
			#1;
			req_i[0] = 1;
			while(!ack_o[0])	@(posedge clk);
			#1;
			req_i[0] = 0;
		   end
	   end

	   begin	// Hardware Handshake Channel 1
		repeat(5)	@(posedge clk);
		for(m1=0;m1 < (k + rest_del_t + 1);m1=m1+1)
		   begin
			repeat(del)	@(posedge clk);
			#1;
			req_i[1] = 1;
			while(!ack_o[1])	@(posedge clk);
			#1;
			req_i[1] = 0;
//$display("m1=%0d",m1);
			if( (do_rest==1) & (m1==rest_del_t) )
			//if( do_rest==1 )
			   begin
//$display("Asserting Restart ...");
				@(posedge clk);
				#1;
				rest_i[1] = 1;
				@(posedge clk);
				#1;
				rest_i[1] = 0;
				do_rest = 0;
				@(posedge clk);
				@(posedge clk);
			   end

		   end
	   end

	   begin	// Hardware Handshake Channel 2
		repeat(5)	@(posedge clk);
		for(m2=0;m2 < k;m2=m2+1)
		   begin
			repeat(del)	@(posedge clk);
			#1;
			req_i[2] = 1;
			while(!ack_o[2])	@(posedge clk);
			#1;
			req_i[2] = 0;
		   end
	   end

	   begin	// Hardware Handshake Channel 3
		repeat(5)	@(posedge clk);
		for(m3=0;m3 < k;m3=m3+1)
		   begin
			repeat(del)	@(posedge clk);
			#1;
			req_i[3] = 1;
			while(!ack_o[3])	@(posedge clk);
			#1;
			req_i[3] = 0;
		   end
	   end

	   for(i=0;i<4;i=i)
	   begin
		repeat(5)	@(posedge clk);
		while(!inta_o)	@(posedge clk);
		m0.wb_rd1(`REG_BASE + `INT_SRCA, 4'hf, int_src);
	
		if(int_src[0])
		   begin
			m0.wb_rd1(`REG_BASE + `CH0_CSR, 4'hf, d0);
			i=i+1;
			for(n=0;n<tot_sz*2;n=n+1)
			   begin
				if(mode[1])	d0=s1.mem[(s0.mem[1]>>2) + n ];
				else		d0=s0.mem[(s0.mem[1]>>2) + n ];
				if(mode[0])	d1=s1.mem[(s0.mem[2]>>2) + n ];
				else		d1=s0.mem[(s0.mem[2]>>2) + n ];
			
				if( d1 !== d0 )
				   begin
					$display("ERROR: CH0: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",
					n, d0, d1, $time);
					error_cnt = error_cnt + 1;
				   end
			   end
		   end

		if(int_src[1])
		   begin
			m0.wb_rd1(`REG_BASE + `CH1_CSR, 4'hf, d0);
			i=i+1;
			for(n=0;n<tot_sz*2;n=n+1)
			   begin
				if(mode[1])	d0=s1.mem[(s0.mem[9]>>2) + n ];
				else		d0=s0.mem[(s0.mem[9]>>2) + n ];
				if(mode[0])	d1=s1.mem[(s0.mem[10]>>2) + n ];
				else		d1=s0.mem[(s0.mem[10]>>2) + n ];
			
				if( d1 !== d0 )
				   begin
					$display("ERROR: CH1: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",
					n, d0, d1, $time);
					error_cnt = error_cnt + 1;
				   end
			   end
		   end

		if(int_src[2])
		   begin
			m0.wb_rd1(`REG_BASE + `CH2_CSR, 4'hf, d0);
			i=i+1;
			for(n=0;n<tot_sz*2;n=n+1)
			   begin
				if(mode[1])	d0=s1.mem[(s0.mem[17]>>2) + n ];
				else		d0=s0.mem[(s0.mem[17]>>2) + n ];
				if(mode[0])	d1=s1.mem[(s0.mem[18]>>2) + n ];
				else		d1=s0.mem[(s0.mem[18]>>2) + n ];
			
				if( d1 !== d0 )
				   begin
					$display("ERROR: CH2: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",
					n, d0, d1, $time);
					error_cnt = error_cnt + 1;
				   end
			   end
		   end

		if(int_src[3])
		   begin
			m0.wb_rd1(`REG_BASE + `CH3_CSR, 4'hf, d0);
			i=i+1;
			for(n=0;n<tot_sz*2;n=n+1)
			   begin
				if(mode[1])	d0=s1.mem[(s0.mem[25]>>2) + n ];
				else		d0=s0.mem[(s0.mem[25]>>2) + n ];
				if(mode[0])	d1=s1.mem[(s0.mem[26]>>2) + n ];
				else		d1=s0.mem[(s0.mem[26]>>2) + n ];
			
				if( d1 !== d0 )
				   begin
					$display("ERROR: CH3: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",
					n, d0, d1, $time);
					error_cnt = error_cnt + 1;
				   end
			   end
		   end

	   end

	join


/*
	if(ack_cnt != ((tot_sz*2*4*2)+(4*4*2)) )
	   begin
		$display("ERROR: ACK count Mismatch: Expected: %0d, Got: %0d (%0t)",
		((tot_sz*2*4*2)+(4*4*2)), ack_cnt, $time);
		error_cnt = error_cnt + 1;
	   end
*/

	repeat(5)	@(posedge clk);

end
end

	s0.delay = 0;
	s1.delay = 0;

show_errors;
$display("*****************************************************");
$display("*** Test DONE ...                                 ***");
$display("*****************************************************\n\n");
end

endtask