tests.v

DMA的控制器的IP核,和ATA控制器配合,可以实现DMA方式高速传输数据.

	   0: $display("Mode: 0->0, chunk_size: %0d", chunk_sz);
	   1: $display("Mode: 0->1, chunk_size: %0d", chunk_sz);
	   2: $display("Mode: 1->0, chunk_size: %0d", chunk_sz);
	   3: $display("Mode: 1->1, chunk_size: %0d", chunk_sz);
	endcase

	ack_cnt_clr = 1;
	@(posedge clk);
	ack_cnt_clr = 0;

	if(chunk_sz==0)		k = 1;
	else
	   begin
		k = tot_sz/chunk_sz;
		if((k*chunk_sz) != tot_sz)	k = k + 1;
		if((k*chunk_sz) != tot_sz)	odd = 1;
		else				odd = 0;
	   end

	if(chunk_sz==0)		k1 = 4;
	else
	   begin
		k1 = tot_sz/chunk_sz;
		if((k1*chunk_sz) != tot_sz)	k1 = k1 + 1;
		k1 = k1 * 4;
	   end

	k1 = k * 4;
	iz = k;

	fork
	   begin
		repeat(5)	@(posedge clk);
		for(m0=0;m0 < k1+1;m0=m0+1)
		   begin
			repeat(del)	@(posedge clk);
			#1;

			if(m0==iz)	nd_i[0] = 1;
			else
			if(m0==(iz*2))	nd_i[0] = 1;
			else
			if(m0==(iz*3))	nd_i[0] = 1;
			else
			if(m0==(iz*4))	nd_i[0] = 1;
			else		req_i[0] = 1;

			if(nd_i[0]==1)
			   begin
				@(posedge clk);
				#1;
				nd_i[0] = 0;
				repeat(1)	@(posedge clk);
				#1;
				req_i[0] = 1;
			   end

			while(!ack_o[0] & (m0 < k1))	@(posedge clk);
			#1;
			req_i[0] = 0;
			nd_i[0] = 0;
		   end
	   end

	   begin
		repeat(5)	@(posedge clk);
		for(m1=0;m1 < k1;m1=m1+1)
		   begin
			repeat(del)	@(posedge clk);
			#1;
			if(m1==k-1)	nd_i[1] = 1;
			if(m1==(k*2)-1)	nd_i[1] = 1;
			if(m1==(k*3)-1)	nd_i[1] = 1;
			if(m1==(k*4)-1)	nd_i[1] = 1;
			req_i[1] = 1;
			while(!ack_o[1])	@(posedge clk);
			#1;
			req_i[1] = 0;
			nd_i[1] = 0;
		   end
	   end

	   begin
		repeat(5)	@(posedge clk);
		for(m2=0;m2 < k1+1;m2=m2+1)
		   begin
			repeat(del)	@(posedge clk);
			#1;

			if(m2==k)	nd_i[2] = 1;
			else
			if(m2==(k*2))	nd_i[2] = 1;
			else
			if(m2==(k*3))	nd_i[2] = 1;
			else
			if(m2==(k*4))	nd_i[2] = 1;
			else		req_i[2] = 1;

			if(nd_i[2]==1)
			   begin
				@(posedge clk);
				#1;
				nd_i[2] = 0;
				repeat(1)	@(posedge clk);
				#1;
				req_i[2] = 1;
			   end

			while(!ack_o[2] & (m2 < k1))	@(posedge clk);
			#1;
			req_i[2] = 0;
			nd_i[2] = 0;
		   end
	   end


	   begin
		repeat(5)	@(posedge clk);
		for(m3=0;m3 < k1;m3=m3+1)
		   begin
			repeat(del)	@(posedge clk);
			#1;
			if(m3==k-1)	nd_i[3] = 1;
			if(m3==(k*2)-1)	nd_i[3] = 1;
			if(m3==(k*3)-1)	nd_i[3] = 1;
			if(m3==(k*4)-1)	nd_i[3] = 1;
			req_i[3] = 1;
			while(!ack_o[3])	@(posedge clk);
			#1;
			req_i[3] = 0;
			nd_i[3] = 0;
		   end
	   end


	   for(i=0;i<4;i=i)
	   begin
		repeat(5)	@(posedge clk);
		while(!inta_o)	@(posedge clk);
		m0.wb_rd1(`REG_BASE + `INT_SRCA, 4'hf, int_src);
	
		if(int_src[0])
		   begin
			i=i+1;
			for(n=0;n<tot_sz*2;n=n+1)
			   begin
				if(mode[1])	d0=s1.mem[(s0.mem[1]>>2) + n ];
				else		d0=s0.mem[(s0.mem[1]>>2) + n ];
				if(mode[0])	d1=s1.mem[(s0.mem[2]>>2) + n ];
				else		d1=s0.mem[(s0.mem[2]>>2) + n ];
			
				if( d1 !== d0 )
				   begin
					$display("ERROR: CH0: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",
					n, d0, d1, $time);
					error_cnt = error_cnt + 1;
				   end
			   end
			repeat(1)	@(posedge clk);
			d1 = {28'h0064_09b, 1'b1, mode[1:0], 1'b0};
			m0.wb_rd1(`REG_BASE + `CH0_CSR, 4'hf, d0);
			repeat(1)	@(posedge clk);
			if( d1 !== d0 )
			   begin
				$display("ERROR: CH0: CSR Mismatch: Expected: %x, Got: %x (%0t)",
				d1, d0, $time);
				error_cnt = error_cnt + 1;
			   end
		   end

		if(int_src[1])
		   begin
			i=i+1;
			for(n=0;n<tot_sz*2;n=n+1)
			   begin
				if(mode[1])	d0=s1.mem[(s0.mem[17]>>2) + n ];
				else		d0=s0.mem[(s0.mem[17]>>2) + n ];
				if(mode[0])	d1=s1.mem[(s0.mem[18]>>2) + n ];
				else		d1=s0.mem[(s0.mem[18]>>2) + n ];
			
				if( d1 !== d0 )
				   begin
					$display("ERROR: CH1: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",
					n, d0, d1, $time);
					error_cnt = error_cnt + 1;
				   end
			   end
			repeat(1)	@(posedge clk);
			d1 = {28'h0064_09b, 1'b1, mode[1:0], 1'b0};
			m0.wb_rd1(`REG_BASE + `CH1_CSR, 4'hf, d0);
			repeat(1)	@(posedge clk);
			if( d1 !== d0 )
			   begin
				$display("ERROR: CH1: CSR Mismatch: Expected: %x, Got: %x (%0t)",
				d1, d0, $time);
				error_cnt = error_cnt + 1;
			   end
			repeat(1)	@(posedge clk);
			case(chunk_sz)
			   default:	d1 = 32'h0000_00c0;
				3:	d1 = 32'h0000_00be;
				5:	d1 = 32'h0000_00bf;
				6:	d1 = 32'h0000_00be;
				7:	d1 = 32'h0000_00ba;
			endcase
			d0 = s0.mem[16];
			repeat(1)	@(posedge clk);
			if( d1 !== d0 )
			   begin
				$display("ERROR: CH1: DESC_CSR Mismatch: Expected: %x, Got: %x (%0t)",
				d1, d0, $time);
				error_cnt = error_cnt + 1;
			   end
		   end

		if(int_src[2])
		   begin
			i=i+1;
			for(n=0;n<tot_sz*2;n=n+1)
			   begin
				if(mode[1])	d0=s1.mem[(s0.mem[33]>>2) + n ];
				else		d0=s0.mem[(s0.mem[33]>>2) + n ];
				if(mode[0])	d1=s1.mem[(s0.mem[34]>>2) + n ];
				else		d1=s0.mem[(s0.mem[34]>>2) + n ];
			
				if( d1 !== d0 )
				   begin
					$display("ERROR: CH2: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",
					n, d0, d1, $time);
					error_cnt = error_cnt + 1;
				   end
			   end
			repeat(1)	@(posedge clk);
			d1 = {28'h0064_09b, 1'b1, mode[1:0], 1'b0};
			m0.wb_rd1(`REG_BASE + `CH2_CSR, 4'hf, d0);
			repeat(1)	@(posedge clk);
			if( d1 !== d0 )
			   begin
				$display("ERROR: CH2: CSR Mismatch: Expected: %x, Got: %x (%0t)",
				d1, d0, $time);
				error_cnt = error_cnt + 1;
			   end
		   end

		if(int_src[3])
		   begin
			i=i+1;
			for(n=0;n<tot_sz*2;n=n+1)
			   begin
				if(mode[1])	d0=s1.mem[(s0.mem[49]>>2) + n ];
				else		d0=s0.mem[(s0.mem[49]>>2) + n ];
				if(mode[0])	d1=s1.mem[(s0.mem[50]>>2) + n ];
				else		d1=s0.mem[(s0.mem[50]>>2) + n ];
			
				if( d1 !== d0 )
				   begin
					$display("ERROR: CH3: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",
					n, d0, d1, $time);
					error_cnt = error_cnt + 1;
				   end
			   end
			repeat(1)	@(posedge clk);
			d1 = {28'h0064_09b, 1'b1, mode[1:0], 1'b0};
			m0.wb_rd1(`REG_BASE + `CH3_CSR, 4'hf, d0);
			repeat(1)	@(posedge clk);
			if( d1 !== d0 )
			   begin
				$display("ERROR: CH3: CSR Mismatch: Expected: %x, Got: %x (%0t)",
				d1, d0, $time);
				error_cnt = error_cnt + 1;
			   end
			repeat(1)	@(posedge clk);
			case(chunk_sz)
			   default:	d1 = 32'h0000_00c0;
				3:	d1 = 32'h0000_00be;
				5:	d1 = 32'h0000_00bf;
				6:	d1 = 32'h0000_00be;
				7:	d1 = 32'h0000_00ba;
			endcase
			d0 = s0.mem[48];
			repeat(1)	@(posedge clk);
			if( d1 !== d0 )
			   begin
				$display("ERROR: CH3: DESC_CSR Mismatch: Expected: %x, Got: %x (%0t)",
				d1, d0, $time);
				error_cnt = error_cnt + 1;
			   end

		   end

	   end
	join

	// CH0: 528 Acks
	// CH1: 532 Acks
	// CH2: 528 Acks
	// CH3: 532 Acks

	case(chunk_sz)
	   default:	k = 2120;
		3:	k = 2184;
		5:	k = 2152;
		6:	k = 2184;
		7:	k = 2312;
	endcase

	if(ack_cnt != k )
	   begin
		$display("ERROR: ACK count Mismatch: Expected: %0d, Got: %0d (%0t)",
		k, ack_cnt, $time);
		error_cnt = error_cnt + 1;
	   end

	repeat(5)	@(posedge clk);

end

s0.delay = 0;
s1.delay = 0;

show_errors;
$display("*****************************************************");
$display("*** Test DONE ...                                 ***");
$display("*****************************************************\n\n");
end

endtask





task sw_dma1;
input		quick;

integer		quick, tot_sz_max, chunk_sz_max;
reg	[7:0]	mode;
reg	[15:0]	chunk_sz, tot_sz;
integer		n;
reg	[31:0]	d0,d1;

begin
$display("\n\n");
$display("*****************************************************");
$display("*** SW DMA No Buffer (tx & chunk size test) ...   ***");
$display("*****************************************************\n");

case(quick)
	default:
	   begin
		tot_sz_max = 1024;
		chunk_sz_max = 256;
	   end
	 1:
	   begin
		tot_sz_max = 128;
		chunk_sz_max = 64;
	   end
	 2:
	   begin
		tot_sz_max = 32;
		chunk_sz_max = 4;
	   end
endcase

mode = 1;
tot_sz = 2048;
tot_sz = 16;
chunk_sz=4;

for(mode=0;mode<4;mode=mode+1)
for(tot_sz=1;tot_sz<tot_sz_max;tot_sz=tot_sz+1)
begin

if(tot_sz>64)	tot_sz=tot_sz+4;
if(tot_sz>128)	tot_sz=tot_sz+12;
case(mode)
   0: $display("Mode: 0->0, tot_size: %0d", tot_sz);
   1: $display("Mode: 0->1, tot_size: %0d", tot_sz);
   2: $display("Mode: 1->0, tot_size: %0d", tot_sz);
   3: $display("Mode: 1->1, tot_size: %0d", tot_sz);
endcase

for(chunk_sz=0;chunk_sz<chunk_sz_max;chunk_sz=chunk_sz+1)
   begin

	if(chunk_sz==17)	chunk_sz=128;
	if(chunk_sz==129)	chunk_sz=255;

	ack_cnt_clr = 1;
	@(posedge clk);
	ack_cnt_clr = 0;

	s0.fill_mem(1);
	s1.fill_mem(1);

	m0.wb_wr1(`REG_BASE + `INT_MASKA,4'hf,32'hffff_ffff);

	m0.wb_wr1(`REG_BASE + `CH0_TXSZ,4'hf, {chunk_sz, tot_sz});
	m0.wb_wr1(`REG_BASE + `CH0_ADR0,4'hf,32'h0000_0000);
	m0.wb_wr1(`REG_BASE + `CH0_ADR1,4'hf,32'h0000_4000);
	m0.wb_wr1(`REG_BASE + `CH0_CSR,4'hf,
		{12'h0000, 3'b010, 1'b0, 11'h000, 2'b11, mode[1:0], 1'b1});

	repeat(5)	@(posedge clk);
	while(!inta_o)	@(posedge clk);

	m0.wb_rd1(`REG_BASE + `INT_SRCA, 4'hf, d1);
	d0 = 32'h0000_0001;
	if( d1 !== d0 )
	   begin
		$display("ERROR: INT_SRCA Mismatch: Expected: %x, Got: %x (%0t)",
			d0, d1, $time);
		error_cnt = error_cnt + 1;
	   end

	m0.wb_rd1(`REG_BASE + `CH0_CSR, 4'hf, d1);
	d0 = {24'h0064_081, 1'b1, mode[1:0], 1'b0};
	if( d1 !== d0 )
	   begin
		$display("ERROR: CH0_CSR Mismatch: Expected: %x, Got: %x (%0t)",
			d0, d1, $time);
		error_cnt = error_cnt + 1;
	   end

	for(n=0;n<tot_sz;n=n+1)
	   begin
		if(mode[1])	d0=s1.mem[ n ];
		else		d0=s0.mem[ n ];
		if(mode[0])	d1=s1.mem[32'h0000_1000 + n ];
		else		d1=s0.mem[32'h0000_1000 + n ];

		if( d1 !== d0 )
		   begin
			$display("ERROR: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",
			n, d0, d1, $time);
			error_cnt = error_cnt + 1;
		   end
	   end

	if(ack_cnt != ((tot_sz*2)) )
	   begin
		$display("ERROR: ACK count Mismatch: Expected: %0d, Got: %0d (%0t)",
		((tot_sz*2)), ack_cnt, $time);
		error_cnt = error_cnt + 1;
	   end

   end
end

show_errors;
$display("*****************************************************");
$display("*** Test DONE ...                                 ***");
$display("*****************************************************\n\n");
end
endtask



task sw_dma2;
input		quick;

integer		quick, tot_sz_max, chunk_sz_max, max_del;

reg	[7:0]	mode;
reg	[15:0]	chunk_sz, tot_sz;
integer		n;
reg	[31:0]	d0,d1;
integer		del0, del1;

begin
$display("\n\n");
$display("*****************************************************");
$display("*** SW DMA No Buffer (slave delay slide) ...      ***");
$display("*****************************************************\n");

case(quick)
	default:
	   begin
		max_del =  6;
		tot_sz_max = 256;
		chunk_sz_max = 16;
	   end
	 1:
	   begin
		max_del =  4;
		tot_sz_max = 128;
		chunk_sz_max = 8;
	   end
	 2:
	   begin
		max_del =  2;
		tot_sz_max = 32;
		chunk_sz_max = 4;
	   end
endcase

mode = 0;
tot_sz = 2048;
tot_sz = 16;
chunk_sz=4;

for(del0=0;del0<max_del;del0=del0+1)
for(del1=0;del1<max_del;del1=del1+1)
for(mode=0;mode<4;mode=mode+1)
for(tot_sz=1;tot_sz<tot_sz_max;tot_sz=tot_sz+4)
begin

if(del0==5)	del0=8;
if(del1==5)	del1=8;

if(tot_sz>128)			tot_sz=tot_sz+4;

$write("Slv 0 delay: %0d, Slv 1 Delay: %0d - ",del0, del1);
case(mode)
   0: $display("Mode: 0->0, tot_size: %0d", tot_sz);
   1: $display("Mode: 0->1, tot_size: %0d", tot_sz);
   2: $display("Mode: 1->0, tot_size: %0d", tot_sz);
   3: $display("Mode: 1->1, tot_size: %0d", tot_sz);
endcase

for(chunk_sz=0;chunk_sz<chunk_sz_max;chunk_sz=chunk_sz+1)

   begin

	if(quick & (chunk_sz > 4))	chunk_sz = chunk_sz + 1;

	s0.delay = del0;
	s1.delay = del1;

	ack_cnt_clr = 1;
	@(posedge clk);
	ack_cnt_clr = 0;

	s0.fill_mem(1);
	s1.fill_mem(1);
	m0.wb_wr1(`REG_BASE + `INT_MASKB,4'hf,32'hffff_ffff);
	m0.wb_wr1(`REG_BASE + `CH0_TXSZ,4'hf, {chunk_sz, tot_sz});
	m0.wb_wr1(`REG_BASE + `CH0_ADR0,4'hf,32'h0000_0000);
	m0.wb_wr1(`REG_BASE + `CH0_ADR1,4'hf,32'h0000_4000);
	m0.wb_wr1(`REG_BASE + `CH0_CSR,4'hf,
		{12'h0000, 3'b010, 1'b0, 11'h000, 2'b11, mode[1:0], 1'b1});

	repeat(5)	@(posedge clk);
	while(!intb_o)	@(posedge clk);

	m0.wb_rd1(`REG_BASE + `INT_SRCB, 4'hf, d1);
	d0 = 32'h0000_0001;
	if( d1 !== d0 )
	   begin
		$display("ERROR: INT_SRC Mismatch: Expected: %x, Got: %x (%0t)",
			d0, d1, $time);
		error_cnt = error_cnt + 1;
	   end

	m0.wb_rd1(`REG_BASE + `CH0_CSR, 4'hf, d1);
	d0 = {24'h0064_081, 1'b1, mode[1:0], 1'b0};
	if( d1 !== d0 )
	   begin
		$display("ERROR: CH0_CSR Mismatch: Expected: %x, Got: %x (%0t)",
			d0, d1, $time);
		error_cnt = error_cnt + 1;
	   end

	for(n=0;n<tot_sz;n=n+1)
	   begin
		if(mode[1])	d0=s1.mem[ n ];
		else		d0=s0.mem[ n ];
		if(mode[0])	d1=s1.mem[32'h0000_1000 + n ];
		else		d1=s0.mem[32'h0000_1000 + n ];

		if( d1 !== d0 )
		   begin
			$display("ERROR: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",
			n, d0, d1, $time);
			error_cnt = error_cnt + 1;
		   end
	   end


	if(ack_cnt != ((tot_sz*2)) )
	   begin
		$display("ERROR: ACK count Mismatch: Expected: %0d, Got: %0d (%0t)",
		((tot_sz*2)), ack_cnt, $time);
		error_cnt = error_cnt + 1;
	   end


   end
end

s0.delay = 0;
s1.delay = 0;

show_errors;
$display("*****************************************************");
$display("*** Test DONE ...                                 ***");
$display("*****************************************************\n\n");
end
endtask



task pt10_rd;

// Misc Variables
reg	[31:0]	d0,d1,d2,d3;
integer		d,n;

begin
$display("\n");
$display("*****************************************************");
$display("*** Running Path Through 1->0 Read Test ....      ***");
$display("*****************************************************\n");

s0.fill_mem(1);
s1.fill_mem(1);
d=0;
n=16;

for(d=0;d<16;d=d+1)
 begin
   $display("INFO: PT10 RD4, delay %0d",d);
   for(n=0;n<512;n=n+4)
     begin
	m0.wb_rd4(n<<2,4'hf,d,d0,d1,d2,d3);