tests.v

DMA的控制器的IP核,和ATA控制器配合,可以实现DMA方式高速传输数据.

/////////////////////////////////////////////////////////////////////
////                                                             ////
////  DMA Test Cases                                             ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          [e-mail]                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/wb_dma/    ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000 Rudolf Usselmann                         ////
////                    [e-mail]                            ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////

//  CVS Log
//
//  $Id: tests.v,v 1.3 2001/09/07 15:34:36 rudi Exp $
//
//  $Date: 2001/09/07 15:34:36 $
//  $Revision: 1.3 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: tests.v,v $
//               Revision 1.3  2001/09/07 15:34:36  rudi
//
//               Changed reset to active high.
//
//               Revision 1.2  2001/08/15 05:40:29  rudi
//
//               - Changed IO names to be more clear.
//               - Uniquifyed define names to be core specific.
//               - Added Section 3.10, describing DMA restart.
//
//               Revision 1.1  2001/07/29 08:57:02  rudi
//
//
//               1) Changed Directory Structure
//               2) Added restart signal (REST)
//
//               Revision 1.1.1.1  2001/03/19 13:12:39  rudi
//               Initial Release
//
//
//                        

task sw_ext_desc1;
input		quick;

integer		quick, tot_sz_max, chunk_sz_max, del_max;

reg	[7:0]	mode;
reg	[15:0]	tot_sz;
reg	[15:0]	chunk_sz;
integer		ii, n,del;
reg	[31:0]	int_src, d0, d1;

begin
$display("\n\n");
$display("*****************************************************");
$display("*** SW DMA No Buffer Ext. Descr LL ...            ***");
$display("*****************************************************\n");

rst = 1;
repeat(10)	@(posedge clk);
rst = 0;
repeat(10)	@(posedge clk);

if(quick)
   begin
	tot_sz_max = 32;
	del_max = 2;
	chunk_sz_max = 4;
   end
else
   begin
	tot_sz_max = 128;
	del_max = 6;
	chunk_sz_max = 8;
   end


mode = 1;
tot_sz = 64;
chunk_sz=3;
del = 0;

for(del=0;del<del_max;del=del+1)
for(mode=0;mode<4;mode=mode+1)
for(tot_sz=1;tot_sz<tot_sz_max;tot_sz=tot_sz + 1)
begin

if(tot_sz>8)	tot_sz = tot_sz + 2;
if(tot_sz>16)	tot_sz = tot_sz + 2;
if(tot_sz>32)	tot_sz = tot_sz + 12;


for(chunk_sz=0;chunk_sz<chunk_sz_max;chunk_sz=chunk_sz+1)
begin

	case(mode)
	   0: $write("Mode: 0->0, ");
	   1: $write("Mode: 0->1, ");
	   2: $write("Mode: 1->0, ");
	   3: $write("Mode: 1->1, ");
	endcase
	$display("Total Size: %0d, Chunk Size: %0d, Slave Delay: %0d",
		tot_sz, chunk_sz, del);

	ack_cnt_clr = 1;
	@(posedge clk);
	ack_cnt_clr = 0;

	s0.delay = del;
	s1.delay = del;

	s0.fill_mem(1);
	s1.fill_mem(1);

	s0.mem[0] = (32'h000c_0000 | (mode[1:0]<<16)) + tot_sz;
	s0.mem[1] = 32'h0000_0100;
	s0.mem[2] = 32'h0000_0400;
	s0.mem[3] = 32'h0000_0010;

	s0.mem[4] = (32'h001c_0000 | (mode[1:0]<<16)) + tot_sz;
	s0.mem[5] = 32'h0000_0100 + (tot_sz * 4);
	s0.mem[6] = 32'h0000_0400 + (tot_sz * 4);
	s0.mem[7] = 32'h0000_0000;


	s0.mem[8] = (32'h000c_0000 | (mode[1:0]<<16)) + tot_sz;
	s0.mem[9] = 32'h0000_0800;
	s0.mem[10] = 32'h0000_0c00;
	s0.mem[11] = 32'h0000_0030;

	s0.mem[12] = (32'h001c_0000 | (mode[1:0]<<16)) + tot_sz;
	s0.mem[13] = 32'h0000_0800 + (tot_sz * 4);
	s0.mem[14] = 32'h0000_0c00 + (tot_sz * 4);
	s0.mem[15] = 32'h0000_0000;


	m0.wb_wr1(`REG_BASE + `INT_MASKA,4'hf,32'hffff_ffff);

	m0.wb_wr1(`REG_BASE + `PTR0, 4'hf, 32'h0000_0020);
	m0.wb_wr1(`REG_BASE + `CH0_TXSZ,4'hf, {chunk_sz, 12'h0});
	m0.wb_wr1(`REG_BASE + `CH0_ADR0,4'hf,32'h0000_0080);
	m0.wb_wr1(`REG_BASE + `CH0_ADR1,4'hf,32'h0000_4000);

	m0.wb_wr1(`REG_BASE + `CH0_CSR,4'hf,
	{15'h0002, 3'b000, 1'b0, 6'h1, 4'b0011, 2'b00, 1'b1});


	m0.wb_wr1(`REG_BASE + `PTR1, 4'hf, 32'h0000_0000);
	m0.wb_wr1(`REG_BASE + `CH1_TXSZ,4'hf, {chunk_sz, 12'h0});
	m0.wb_wr1(`REG_BASE + `CH1_ADR0,4'hf,32'h0000_0080);
	m0.wb_wr1(`REG_BASE + `CH1_ADR1,4'hf,32'h0000_4000);

	m0.wb_wr1(`REG_BASE + `CH1_CSR,4'hf,
	{15'h0002, 3'b000, 1'b0, 6'h1, 4'b0011, 2'b00, 1'b1});


for(ii=0;ii<2;ii=ii+1)
begin
	repeat(5)	@(posedge clk);
	while(!inta_o)	@(posedge clk);

	m0.wb_rd1(`REG_BASE + `INT_SRCA, 4'hf, int_src);

	if(int_src[0])
	begin
	for(n=0;n<tot_sz*2;n=n+1)
	   begin
		if(mode[1])	d0=s1.mem[(s0.mem[9]>>2) + n ];
		else		d0=s0.mem[(s0.mem[9]>>2) + n ];
		if(mode[0])	d1=s1.mem[(s0.mem[10]>>2) + n ];
		else		d1=s0.mem[(s0.mem[10]>>2) + n ];
	
		if( d1 !== d0 )
		   begin
			$display("ERROR: CH0: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",
			n, d0, d1, $time);
			error_cnt = error_cnt + 1;
		   end
	   end
	m0.wb_rd1(`REG_BASE + `CH0_CSR, 4'hf, d1);
	d0 = {24'h0064_089, 1'b1, mode[1:0], 1'b0};
	if( d1 !== d0 )
	   begin
		$display("ERROR: CH0_CSR Mismatch: Expected: %x, Got: %x (%0t)",
			d0, d1, $time);
		error_cnt = error_cnt + 1;
	   end
	end


	if(int_src[1])
	begin
	for(n=0;n<tot_sz*2;n=n+1)
	   begin
		if(mode[1])	d0=s1.mem[(s0.mem[1]>>2) + n ];
		else		d0=s0.mem[(s0.mem[1]>>2) + n ];
		if(mode[0])	d1=s1.mem[(s0.mem[2]>>2) + n ];
		else		d1=s0.mem[(s0.mem[2]>>2) + n ];
	
		if( d1 !== d0 )
		   begin
			$display("ERROR: CH1: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",
			n, d0, d1, $time);
			error_cnt = error_cnt + 1;
		   end
	   end
	m0.wb_rd1(`REG_BASE + `CH1_CSR, 4'hf, d1);
	d0 = {24'h0064_089, 1'b1, mode[1:0], 1'b0};
	if( d1 !== d0 )
	   begin
		$display("ERROR: CH1_CSR Mismatch: Expected: %x, Got: %x (%0t)",
			d0, d1, $time);
		error_cnt = error_cnt + 1;
	   end
	end

end

	if(ack_cnt != ((tot_sz*4)+(4*2))*2 )
	   begin
		$display("ERROR: ACK count Mismatch: Expected: %0d, Got: %0d (%0t)",
		((tot_sz*4)+(4*2)), ack_cnt, $time);
		error_cnt = error_cnt + 1;
	   end

	repeat(5)	@(posedge clk);

end
end

show_errors;
$display("*****************************************************");
$display("*** Test DONE ...                                 ***");
$display("*****************************************************\n\n");
end


endtask



task arb_test1;

reg	[7:0]	mode;
reg	[15:0]	tot_sz;
reg	[15:0]	chunk_sz0;
reg	[15:0]	chunk_sz1;
reg	[15:0]	chunk_sz2;
reg	[15:0]	chunk_sz3;
integer		a,n,ptr;
reg	[31:0]	d0,d1;
reg	[7:0]	pri, order, finish;

begin
$display("\n\n");
$display("*****************************************************");
$display("*** SW DMA No Buffer 4 ch pri ...                 ***");
$display("*****************************************************\n");

mode = 0;
tot_sz = 32;
chunk_sz0=4;
chunk_sz1=4;
chunk_sz2=4;
chunk_sz3=4;
a=0;

m0.wb_wr1(`REG_BASE + `CH0_CSR,4'hf, 32'h0);
m0.wb_wr1(`REG_BASE + `CH1_CSR,4'hf, 32'h0);
m0.wb_wr1(`REG_BASE + `CH2_CSR,4'hf, 32'h0);
m0.wb_wr1(`REG_BASE + `CH3_CSR,4'hf, 32'h0);

m0.wb_rd1(`REG_BASE + `INT_SRCA, 4'hf, d0);

for(mode=0;mode<4;mode=mode+1)
for(a=0;a<17;a=a+1)
begin

	chunk_sz0=4;
	chunk_sz1=4;
	chunk_sz2=4;
	chunk_sz3=4;

	s0.delay = 0;
	s1.delay = 0;

	case(a)		// ch3 ch2 ch1 ch0
	   0:
	     begin
		pri = 8'b10_10_10_10;	// All equal 0,1,2,3
		order = {2'd0, 2'd1, 2'd2, 2'd3};
	     end

		// One channel with High Priority
		// The other depend oon the ARB state
	   1:
	     begin
		pri = 8'b00_00_00_10;	// 3,1,0,2
		order = {2'b0, 2'd3, 2'd1, 2'd2};
	     end
	   2:
	     begin
		pri = 8'b00_00_10_00;	// 2,3,0,1
		order = {2'd1, 2'd0, 2'd2, 2'd3};
	     end
	   3:
	     begin
		pri = 8'b00_10_00_00;	// 1,0,2,3
		order = {2'd2, 2'd0, 2'd1, 2'd3};
	     end
	   4:
	     begin
		pri = 8'b10_00_00_00;	// 0,3,1,2
		order = {2'd3, 2'd0, 2'd1, 2'd2};
	     end

		// Specific order for all Channels
	   5:
	     begin
		pri = 8'b10_00_01_11;	// 3,0,2,1
		order = {2'd0, 2'd3, 2'd1, 2'd2};
	     end

	   6:
	     begin
		pri = 8'b00_10_11_01;	// 2,1,3,0
		order = {2'd1, 2'd2, 2'd0, 2'd3};
	     end

	   7:
	     begin
		pri = 8'b00_11_01_10;	// 1,3,2,0
		order = {2'd2, 2'd0, 2'd1, 2'd3};
	     end

	   8:
	     begin
		pri = 8'b00_01_10_11;	// 3,2,1,0
		order = {2'd0, 2'd1, 2'd2, 2'd3};
	     end

		// One channel with High Priority
		// The other depend oon the ARB state
		// Chunk Size varies
		// First channel small chunkc size
	   9:
	     begin
		pri = 8'b00_00_00_10;	// 3,1,0,2
		order = {2'd0, 2'd1, 2'd2, 2'd3};
		chunk_sz3=1;
	     end
	   10:
	     begin
		pri = 8'b00_00_10_00;	// 2,0,1,3
		order = {2'd1, 2'd0, 2'd3, 2'd2};
		chunk_sz2=1;
	     end
	   11:
	     begin
		pri = 8'b00_10_00_00;	// 1,0,2,3
		order = {2'd2, 2'd0, 2'd3, 2'd1};
		chunk_sz1=1;
	     end
	   12:
	     begin
		pri = 8'b10_00_00_00;	// 0,2,3,1
		order = {2'd3, 2'd1, 2'd2, 2'd0};
		chunk_sz0=1;
	     end

		// First channel large chunkc size
	   13:
	     begin
		pri = 8'b00_00_00_10;	// 3,0,2,1
		order = {2'd0, 2'd3, 2'd1, 2'd2};
		chunk_sz3=8;
	     end
	   14:
	     begin
		pri = 8'b00_00_10_00;	// 2,0,3,1
		order = {2'd1, 2'd2, 2'd0, 2'd3};
		chunk_sz2=8;
	     end
	   15:
	     begin
		pri = 8'b00_10_00_00;	// 1,0,3,2
		order = {2'd2, 2'd1, 2'd0, 2'd3};
		chunk_sz1=8;
	     end
	   16:
	     begin
		pri = 8'b10_00_00_00;	// 0,2,3,1
		order = {2'd3, 2'd0, 2'd1, 2'd2};
		chunk_sz0=8;
	     end

	endcase

case(mode)
   0: $write("Mode: 0->0, ");
   1: $write("Mode: 0->1, ");
   2: $write("Mode: 1->0, ");
   3: $write("Mode: 1->1, ");
endcase
$display("a: %0d", a);

	ack_cnt_clr = 1;
	@(posedge clk);
	ack_cnt_clr = 0;

	s0.fill_mem(1);
	s1.fill_mem(1);

	m0.wb_wr1(`REG_BASE + `CH0_CSR,4'hf,
		{17'h00000, pri[1:0], 6'h0, 4'b0011, mode[1:0], 1'b0});

	m0.wb_wr1(`REG_BASE + `CH1_CSR,4'hf,
		{17'h00000, pri[3:2], 6'h0, 4'b0011, mode[1:0], 1'b0});

	m0.wb_wr1(`REG_BASE + `CH2_CSR,4'hf,
		{17'h00000, pri[5:4], 6'h0, 4'b0011, mode[1:0], 1'b0});

	m0.wb_wr1(`REG_BASE + `CH3_CSR,4'hf,
		{17'h00000, pri[7:6], 6'h0, 4'b0011, mode[1:0], 1'b0});

	m0.wb_wr1(`REG_BASE + `INT_MASKA,4'hf,32'hffff_ffff);

	m0.wb_wr1(`REG_BASE + `CH0_TXSZ,4'hf, {chunk_sz0, tot_sz});
	m0.wb_wr1(`REG_BASE + `CH0_ADR0,4'hf,32'h0000_0000);
	m0.wb_wr1(`REG_BASE + `CH0_ADR1,4'hf,32'h0000_4000);

	m0.wb_wr1(`REG_BASE + `CH1_TXSZ,4'hf, {chunk_sz1, tot_sz});
	m0.wb_wr1(`REG_BASE + `CH1_ADR0,4'hf,32'h0000_0080);
	m0.wb_wr1(`REG_BASE + `CH1_ADR1,4'hf,32'h0000_4080);

	m0.wb_wr1(`REG_BASE + `CH2_TXSZ,4'hf, {chunk_sz2, tot_sz});
	m0.wb_wr1(`REG_BASE + `CH2_ADR0,4'hf,32'h0000_0100);
	m0.wb_wr1(`REG_BASE + `CH2_ADR1,4'hf,32'h0000_4100);

	m0.wb_wr1(`REG_BASE + `CH3_TXSZ,4'hf, {chunk_sz3, tot_sz});
	m0.wb_wr1(`REG_BASE + `CH3_ADR0,4'hf,32'h0000_0180);
	m0.wb_wr1(`REG_BASE + `CH3_ADR1,4'hf,32'h0000_4180);


	m0.wb_wr1(`REG_BASE + `CH0_CSR,4'hf,
		{12'h000, 3'b010, 1'b0, 1'b0, pri[1:0], 6'h0, 4'b0011, mode[1:0], 1'b1});

	        //{15'h0002, 3'b000, 1'b0, 6'h1, 4'b0011, 2'b00, 1'b1});

	m0.wb_wr1(`REG_BASE + `CH1_CSR,4'hf,
		{12'h000, 3'b010, 1'b0, 1'b0, pri[3:2], 6'h0, 4'b0011, mode[1:0], 1'b1});

	m0.wb_wr1(`REG_BASE + `CH2_CSR,4'hf,
		{12'h000, 3'b010, 1'b0, 1'b0, pri[5:4], 6'h0, 4'b0011, mode[1:0], 1'b1});



	m0.wb_wr1(`REG_BASE + `CH3_CSR,4'hf,
		{12'h0000, 3'b010, 1'b0, 1'b0, pri[7:6], 6'h0, 4'b0011, mode[1:0], 1'b1});

	repeat(1)	@(posedge clk);

	// Wait for interrupt, Check completion order

	ptr=0;
	finish = 8'hxx;

	while(ptr!=4)
	   begin
		while(!inta_o)	@(posedge clk);
		m0.wb_rd1(`REG_BASE + `INT_SRCA, 4'hf, d0);

		if(d0[0])	d0[1:0] = 0;
		else
		if(d0[1])	d0[1:0] = 1;
		else
		if(d0[2])	d0[1:0] = 2;
		else
		if(d0[3])	d0[1:0] = 3;

		case(ptr)
		   0: finish[7:6] = d0[1:0];
		   1: finish[5:4] = d0[1:0];
		   2: finish[3:2] = d0[1:0];
		   3: finish[1:0] = d0[1:0];
		endcase

		case(d0[1:0])
		   0: m0.wb_rd1(`REG_BASE + `CH0_CSR, 4'hf, d0);
		   1: m0.wb_rd1(`REG_BASE + `CH1_CSR, 4'hf, d0);
		   2: m0.wb_rd1(`REG_BASE + `CH2_CSR, 4'hf, d0);
		   3: m0.wb_rd1(`REG_BASE + `CH3_CSR, 4'hf, d0);
		endcase

		ptr=ptr+1;
		repeat(4)	@(posedge clk);
	   end


	if(finish !== order)
	   begin
		$display("ERROR: Completion Order[%0d] Mismatch: Expected: %b, Got: %b (%0t)",
		a, order, finish, $time);
		error_cnt = error_cnt + 1;
	   end


	for(n=0;n<tot_sz*4;n=n+1)
	   begin
		if(mode[1])	d0=s1.mem[ n ];
		else		d0=s0.mem[ n ];
		if(mode[0])	d1=s1.mem[32'h0000_1000 + n ];
		else		d1=s0.mem[32'h0000_1000 + n ];
	
		if( d1 !== d0 )
		   begin
			$display("ERROR: Data[%0d] Mismatch: Expected: %x, Got: %x (%0t)",
			n, d0, d1, $time);
			error_cnt = error_cnt + 1;
		   end
	   end

	if(ack_cnt != ((tot_sz*4*2)) )
	   begin
		$display("ERROR: ACK count Mismatch: Expected: %0d, Got: %0d (%0t)",
		((tot_sz*4)), ack_cnt, $time);
		error_cnt = error_cnt + 1;
	   end


	repeat(5)	@(posedge clk);

end

show_errors;
$display("*****************************************************");
$display("*** Test DONE ...                                 ***");
$display("*****************************************************\n\n");
end

endtask






task hw_dma1;
input	quick;

integer		quick, chunk_sz_max, del_max;

reg	[7:0]	mode;
reg	[15:0]	chunk_sz, tot_sz;
integer		n,m,k,rep,del;
reg	[31:0]	d0,d1;

begin
$display("\n\n");
$display("*****************************************************");
$display("*** HW DMA No Buffer ...                          ***");
$display("*****************************************************\n");

if(quick)
   begin
	tot_sz = 32;
	chunk_sz_max= 4;
	del_max = 3;
   end
else
   begin
	tot_sz = 64;
	chunk_sz_max= 8;
	del_max = 5;
   end

mode = 1;
chunk_sz=4;
del = 8;
for(mode=0;mode<4;mode=mode+1)
for(chunk_sz=0;chunk_sz<chunk_sz_max;chunk_sz=chunk_sz+1)
for(del=0;del<del_max;del=del+1)
begin

	m0.wb_wr1(`REG_BASE + `INT_MASKA,4'hf,32'h0000_ffff);
	m0.wb_wr1(`REG_BASE + `CH0_TXSZ,4'hf, {chunk_sz, tot_sz});
	m0.wb_wr1(`REG_BASE + `CH0_ADR0,4'hf,32'h0000_0000);
	m0.wb_wr1(`REG_BASE + `CH0_ADR1,4'hf,32'h0000_4000);
	m0.wb_wr1(`REG_BASE + `CH0_CSR,4'hf,
		{25'h0000000, 4'b1111, mode[1:0], 1'b1});

$write("Delay: %0d ",del);
case(mode)
   0: $display("Mode: 0->0, chunk_size: %0d", chunk_sz);
   1: $display("Mode: 0->1, chunk_size: %0d", chunk_sz);
   2: $display("Mode: 1->0, chunk_size: %0d", chunk_sz);
   3: $display("Mode: 1->1, chunk_size: %0d", chunk_sz);