revision_history.txt

ATA接口的IP核,经过量产的验证,已经在quartus5.1下编译通过了.

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Revision: 1.0
Date: June 28th, 2001
Author: Richard Herveille
- Initial Verilog release (beta)
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Revision: 1.1
Date: June 18th, 2001
Author: Richard Herveille
- Fixed some incomplete port lists and some Verilog related issues.
  Design now completely compiles
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Revision: 1.1a
Date: July 3rd, 2001
Author: Richard Herveille
- Rewrote some sections (controller.v, ata.v). Minor Verilog coding styles issues.
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Revision: 1.2
Date: July 9th, 2001
Author: Richard Herveille
- added 'timescale to all files
- fixed error where control registers latched data on all rising clock edges, instead of
  when addressed.
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Revision: 1.3
Date: July 11th, 2001
Author: Richard Herveille
- Fixed case sensitivity error (nRESET instead of nReset) in "controller" module declaration.
- changed 'ata.v' into 'atahost.v'
- Changed PIOreq & PIOack generation (controller.vhd); made them synchronous
- Changed 'go' & 'igo' generation (pio_tctrl.vhdl).
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Revision: 1.4
Date: July 26th, 2001
Author: Richard Herveille
- Fixed some blocking versus non-blocking statement issues.
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Revision: 1.5
Date: August 15th, 2001.
Author: Richard Herveille
- Changed filenames and top-level port names to be conform new OpenCores conventions
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Revision: 1.6
Date: September 12th, 2001.
Author: Richard Herveille
- Made asynchronous input programmable (using atahost_define.v)
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Revision: 1.7
Date: October 16th, 2001.
Author: Richard Herveille
- Changed programmable asynchronous level from define to parameter
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Revision: 1.8
Date: Februar 16th, 2002.
Author: Richard Herveille
- Added disclaimer
- Added CVS information
- Changed core for new counter libraries
- Updated testbench
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Revision: 1.9
Date: Februar 17th, 2002.
Author: Richard Herveille
- moved wishbone interface into 'atahost_wb_slave.v'
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Revision: 1.10
Date: May 19th, 2002.
Author: Richard Herveille
- Fixed a potential bug that forced the core into an unknown state
  when an asynchronous reset was given without a running clock
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