atahost_wb_slave.v

ATA接口的IP核,经过量产的验证,已经在quartus5.1下编译通过了.

			store_pp_full <= #1 PIOpp_full;

	wire brty = (`ATA_DEV_ADR & w_acc) & (DMAtip | store_pp_full);

	//
	// generate registers
	//

	// generate register select signals
	wire sel_ctrl        = CONsel & we_i & (`ATA_ADR == `ATA_CTRL_REG);
	wire sel_stat        = CONsel & we_i & (`ATA_ADR == `ATA_STAT_REG);
	wire sel_PIO_cmdport = CONsel & we_i & (`ATA_ADR == `ATA_PIO_CMD);
	wire sel_PIO_dport0  = CONsel & we_i & (`ATA_ADR == `ATA_PIO_DP0);
	wire sel_PIO_dport1  = CONsel & we_i & (`ATA_ADR == `ATA_PIO_DP1);
	wire sel_DMA_dev0    = CONsel & we_i & (`ATA_ADR == `ATA_DMA_DEV0);
	wire sel_DMA_dev1    = CONsel & we_i & (`ATA_ADR == `ATA_DMA_DEV1);
	// reserved 0x1c-0x38
	// reserved 0x3c : DMA-port


	// generate control register
	always@(posedge clk_i or negedge arst_i)
		if (~arst_i)
			begin
				CtrlReg[31:1] <= #1 0;
				CtrlReg[0]    <= #1 1'b1; // set reset bit (ATA-RESETn line)
			end
		else if (rst_i)
			begin
				CtrlReg[31:1] <= #1 0;
				CtrlReg[0]    <= #1 1'b1; // set reset bit (ATA-RESETn line)
			end
		else if (sel_ctrl)
			CtrlReg <= #1 dat_i;

	// assign bits
	assign DMActrl_DMAen        = CtrlReg[15];
	assign DMActrl_dir          = CtrlReg[13];
	assign DMActrl_BeLeC1       = CtrlReg[9];
	assign DMActrl_BeLeC0       = CtrlReg[8];
	assign IDEctrl_IDEen        = CtrlReg[7];
	assign IDEctrl_FATR1        = CtrlReg[6];
	assign IDEctrl_FATR0        = CtrlReg[5];
	assign IDEctrl_ppen         = CtrlReg[4];
	assign PIO_dport1_IORDYen   = CtrlReg[3];
	assign PIO_dport0_IORDYen   = CtrlReg[2];
	assign PIO_cmdport_IORDYen  = CtrlReg[1];
	assign IDEctrl_rst          = CtrlReg[0];


	// generate status register clearable bits
	reg dirq, int;
	
	always@(posedge clk_i or negedge arst_i)
		if (~arst_i)
			begin
				int  <= #1 1'b0;
				dirq <= #1 1'b0;
			end
		else if (rst_i)
			begin
				int  <= #1 1'b0;
				dirq <= #1 1'b0;
			end
		else
			begin
				int  <= #1 (int | (irq & !dirq)) & !(sel_stat & !dat_i[0]);
				dirq <= #1 irq;
			end

	// assign status bits
	assign StatReg[31:28] = DeviceId;   // set Device ID
	assign StatReg[27:24] = RevisionNo; // set revision number
	assign StatReg[23:16] = 0;          // reserved
	assign StatReg[15]    = DMAtip;
	assign StatReg[14:11] = 0;
	assign StatReg[10]    = DMARxEmpty;
	assign StatReg[9]     = DMATxFull;
	assign StatReg[8]     = DMA_dmarq;
	assign StatReg[7]     = PIOtip;
	assign StatReg[6]     = PIOpp_full;
	assign StatReg[5:1]   = 0;          // reserved
	assign StatReg[0]     = int;


	// generate PIO compatible / command-port timing register
	always@(posedge clk_i or negedge arst_i)
		if (~arst_i)
			begin
				PIO_cmdport_T1   <= #1 PIO_mode0_T1;
				PIO_cmdport_T2   <= #1 PIO_mode0_T2;
				PIO_cmdport_T4   <= #1 PIO_mode0_T4;
				PIO_cmdport_Teoc <= #1 PIO_mode0_Teoc;
			end
		else if (rst_i)
			begin
				PIO_cmdport_T1   <= #1 PIO_mode0_T1;
				PIO_cmdport_T2   <= #1 PIO_mode0_T2;
				PIO_cmdport_T4   <= #1 PIO_mode0_T4;
				PIO_cmdport_Teoc <= #1 PIO_mode0_Teoc;
			end
		else if(sel_PIO_cmdport)
			begin
				PIO_cmdport_T1   <= #1 dat_i[ 7: 0];
				PIO_cmdport_T2   <= #1 dat_i[15: 8];
				PIO_cmdport_T4   <= #1 dat_i[23:16];
				PIO_cmdport_Teoc <= #1 dat_i[31:24];
			end

	// generate PIO device0 timing register
	always@(posedge clk_i or negedge arst_i)
		if (~arst_i)
			begin
				PIO_dport0_T1   <= #1 PIO_mode0_T1;
				PIO_dport0_T2   <= #1 PIO_mode0_T2;
				PIO_dport0_T4   <= #1 PIO_mode0_T4;
				PIO_dport0_Teoc <= #1 PIO_mode0_Teoc;
			end
		else if (rst_i)
			begin
				PIO_dport0_T1   <= #1 PIO_mode0_T1;
				PIO_dport0_T2   <= #1 PIO_mode0_T2;
				PIO_dport0_T4   <= #1 PIO_mode0_T4;
				PIO_dport0_Teoc <= #1 PIO_mode0_Teoc;
			end
		else if(sel_PIO_dport0)
			begin
				PIO_dport0_T1   <= #1 dat_i[ 7: 0];
				PIO_dport0_T2   <= #1 dat_i[15: 8];
				PIO_dport0_T4   <= #1 dat_i[23:16];
				PIO_dport0_Teoc <= #1 dat_i[31:24];
			end

	// generate PIO device1 timing register
	always@(posedge clk_i or negedge arst_i)
		if (~arst_i)
			begin
				PIO_dport1_T1   <= #1 PIO_mode0_T1;
				PIO_dport1_T2   <= #1 PIO_mode0_T2;
				PIO_dport1_T4   <= #1 PIO_mode0_T4;
				PIO_dport1_Teoc <= #1 PIO_mode0_Teoc;
			end
		else if (rst_i)
			begin
				PIO_dport1_T1   <= #1 PIO_mode0_T1;
				PIO_dport1_T2   <= #1 PIO_mode0_T2;
				PIO_dport1_T4   <= #1 PIO_mode0_T4;
				PIO_dport1_Teoc <= #1 PIO_mode0_Teoc;
			end
		else if(sel_PIO_dport1)
			begin
				PIO_dport1_T1   <= #1 dat_i[ 7: 0];
				PIO_dport1_T2   <= #1 dat_i[15: 8];
				PIO_dport1_T4   <= #1 dat_i[23:16];
				PIO_dport1_Teoc <= #1 dat_i[31:24];
			end

	// generate DMA device0 timing register
	always@(posedge clk_i or negedge arst_i)
		if (~arst_i)
			begin
				DMA_dev0_Tm   <= #1 DMA_mode0_Tm;
				DMA_dev0_Td   <= #1 DMA_mode0_Td;
				DMA_dev0_Teoc <= #1 DMA_mode0_Teoc;
			end
		else if (rst_i)
			begin
				DMA_dev0_Tm   <= #1 DMA_mode0_Tm;
				DMA_dev0_Td   <= #1 DMA_mode0_Td;
				DMA_dev0_Teoc <= #1 DMA_mode0_Teoc;
			end
		else if(sel_DMA_dev0)
			begin
				DMA_dev0_Tm   <= #1 dat_i[ 7: 0];
				DMA_dev0_Td   <= #1 dat_i[15: 8];
				DMA_dev0_Teoc <= #1 dat_i[31:24];
			end

	// generate DMA device1 timing register
	always@(posedge clk_i or negedge arst_i)
		if (~arst_i)
			begin
				DMA_dev1_Tm   <= #1 DMA_mode0_Tm;
				DMA_dev1_Td   <= #1 DMA_mode0_Td;
				DMA_dev1_Teoc <= #1 DMA_mode0_Teoc;
			end
		else if (rst_i)
			begin
				DMA_dev1_Tm   <= #1 DMA_mode0_Tm;
				DMA_dev1_Td   <= #1 DMA_mode0_Td;
				DMA_dev1_Teoc <= #1 DMA_mode0_Teoc;
			end
		else if(sel_DMA_dev1)
			begin
				DMA_dev1_Tm   <= #1 dat_i[ 7: 0];
				DMA_dev1_Td   <= #1 dat_i[15: 8];
				DMA_dev1_Teoc <= #1 dat_i[31:24];
			end

	//
	// generate WISHBONE interconnect signals
	//
	reg [31:0] Q;

	// generate acknowledge signal
	assign ack_o = PIOack | CONsel; // | DMAack; // since DMAack is derived from CONsel this is OK

	// generate error signal
	assign err_o = cyc_i & stb_i & berr;

	// generate retry signal (for OCIDEC-3 and above only)
	assign rty_o = cyc_i & stb_i & brty;

	// generate interrupt signal
	assign inta_o = StatReg[0];
	
	// generate output multiplexor
	always@(`ATA_ADR or CtrlReg or StatReg or 
			PIO_cmdport_T1 or PIO_cmdport_T2 or PIO_cmdport_T4 or PIO_cmdport_Teoc or
			PIO_dport0_T1 or PIO_dport0_T2 or PIO_dport0_T4 or PIO_dport0_Teoc or
			PIO_dport1_T1 or PIO_dport1_T2 or PIO_dport1_T4 or PIO_dport1_Teoc or
			DMA_dev0_Tm or DMA_dev0_Td or DMA_dev0_Teoc or
			DMA_dev1_Tm or DMA_dev1_Td or DMA_dev1_Teoc or
			DMAq
		)
		case (`ATA_ADR) // synopsis full_case parallel_case
			`ATA_CTRL_REG: Q = CtrlReg;
			`ATA_STAT_REG: Q = StatReg;
			`ATA_PIO_CMD : Q = {PIO_cmdport_Teoc, PIO_cmdport_T4, PIO_cmdport_T2, PIO_cmdport_T1};
			`ATA_PIO_DP0 : Q = {PIO_dport0_Teoc, PIO_dport0_T4, PIO_dport0_T2, PIO_dport0_T1};
			`ATA_PIO_DP1 : Q = {PIO_dport1_Teoc, PIO_dport1_T4, PIO_dport1_T2, PIO_dport1_T1};
			`ATA_DMA_DEV0: Q = {DMA_dev0_Teoc, 8'h0, DMA_dev0_Td, DMA_dev0_Tm};
			`ATA_DMA_DEV1: Q = {DMA_dev1_Teoc, 8'h0, DMA_dev1_Td, DMA_dev1_Tm};
			`ATA_DMA_PORT: Q = DMAq;
			default: Q = 0;
		endcase

	// assign DAT_O output
	assign dat_o = `ATA_DEV_ADR ? {16'h0, PIOq} : Q;

endmodule