stm32l1xx_rcc.c

STM32+Grlib

  *     @arg RCC_MSIRange_0: MSI clock is around 65.536 KHz
  *     @arg RCC_MSIRange_1: MSI clock is around 131.072 KHz
  *     @arg RCC_MSIRange_2: MSI clock is around 262.144 KHz
  *     @arg RCC_MSIRange_3: MSI clock is around 524.288 KHz
  *     @arg RCC_MSIRange_4: MSI clock is around 1.048 MHz
  *     @arg RCC_MSIRange_5: MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY)
  *     @arg RCC_MSIRange_6: MSI clock is around 
  *                   
  * @retval None
  */
void RCC_MSIRangeConfig(uint32_t RCC_MSIRange)
{
  uint32_t tmpreg = 0;
  
  /* Check the parameters */
  assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_MSIRange));
  
  tmpreg = RCC->ICSCR;
  
  /* Clear MSIRANGE[2:0] bits */
  tmpreg &= ~RCC_ICSCR_MSIRANGE;
  
  /* Set the MSIRANGE[2:0] bits according to RCC_MSIRange value */
  tmpreg |= (uint32_t)RCC_MSIRange;

  /* Store the new value */
  RCC->ICSCR = tmpreg;
}

/**
  * @brief  Enables or disables the Internal Multi Speed oscillator (MSI).
  * @note   - The MSI is stopped by hardware when entering STOP and STANDBY modes.
  *           It is used (enabled by hardware) as system clock source after
  *           startup from Reset, wakeup from STOP and STANDBY mode, or in case
  *           of failure of the HSE used directly or indirectly as system clock
  *           (if the Clock Security System CSS is enabled).             
  *         - MSI can not be stopped if it is used as system clock source.
  *           In this case, you have to select another source of the system
  *           clock then stop the MSI.  
  *         - After enabling the MSI, the application software should wait on
  *           MSIRDY flag to be set indicating that MSI clock is stable and can
  *           be used as system clock source.                                       
  * @param  NewState: new state of the MSI.
  *   This parameter can be: ENABLE or DISABLE.
  * @note   When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator
  *         clock cycles.  
  * @retval None
  */
void RCC_MSICmd(FunctionalState NewState)
{
  /* Check the parameters */
  assert_param(IS_FUNCTIONAL_STATE(NewState));
  
  *(__IO uint32_t *) CR_MSION_BB = (uint32_t)NewState;
}

/**
  * @brief  Adjusts the Internal High Speed oscillator (HSI) calibration value.
  * @note   The calibration is used to compensate for the variations in voltage
  *         and temperature that influence the frequency of the internal HSI RC.
  *         Refer to the Application Note AN3300 for more details on how to  
  *         calibrate the HSI.
  * @param  HSICalibrationValue: specifies the HSI calibration trimming value.
  *   This parameter must be a number between 0 and 0x1F.
  * @retval None
  */
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
{
  uint32_t tmpreg = 0;
  
  /* Check the parameters */
  assert_param(IS_RCC_HSI_CALIBRATION_VALUE(HSICalibrationValue));
  
  tmpreg = RCC->ICSCR;
  
  /* Clear HSITRIM[4:0] bits */
  tmpreg &= ~RCC_ICSCR_HSITRIM;
  
  /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
  tmpreg |= (uint32_t)HSICalibrationValue << 8;

  /* Store the new value */
  RCC->ICSCR = tmpreg;
}

/**
  * @brief  Enables or disables the Internal High Speed oscillator (HSI).
  * @note   - After enabling the HSI, the application software should wait on 
  *           HSIRDY flag to be set indicating that HSI clock is stable and can
  *           be used to clock the PLL and/or system clock.
  *         - HSI can not be stopped if it is used directly or through the PLL
  *           as system clock. In this case, you have to select another source 
  *           of the system clock then stop the HSI.
  *         - The HSI is stopped by hardware when entering STOP and STANDBY modes. 
  * @param  NewState: new state of the HSI.
  *   This parameter can be: ENABLE or DISABLE.
  * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
  *         clock cycles.  
  * @retval None
  */
void RCC_HSICmd(FunctionalState NewState)
{
  /* Check the parameters */
  assert_param(IS_FUNCTIONAL_STATE(NewState));
  
  *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;
}

/**
  * @brief  Configures the External Low Speed oscillator (LSE).
  * @note   - As the LSE is in the RTC domain and write access is denied to this
  *           domain after reset, you have to enable write access using 
  *           PWR_RTCAccessCmd(ENABLE) function before to configure the LSE
  *           (to be done once after reset).  
  *         - After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application
  *           software should wait on LSERDY flag to be set indicating that LSE clock
  *           is stable and can be used to clock the RTC.
  * @param  RCC_LSE: specifies the new state of the LSE.
  *   This parameter can be one of the following values:
  *     @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
  *                       6 LSE oscillator clock cycles.
  *     @arg RCC_LSE_ON: turn ON the LSE oscillator
  *     @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock
  * @retval None
  */
void RCC_LSEConfig(uint8_t RCC_LSE)
{
  /* Check the parameters */
  assert_param(IS_RCC_LSE(RCC_LSE));
  
  /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
  *(__IO uint8_t *) CSR_BYTE2_ADDRESS = RCC_LSE_OFF;

  /* Set the new LSE configuration -------------------------------------------*/
  *(__IO uint8_t *) CSR_BYTE2_ADDRESS = RCC_LSE;  
}

/**
  * @brief  Enables or disables the Internal Low Speed oscillator (LSI).  
  * @note   - After enabling the LSI, the application software should wait on 
  *           LSIRDY flag to be set indicating that LSI clock is stable and can
  *           be used to clock the IWDG and/or the RTC.
  *         - LSI can not be disabled if the IWDG is running.  
  * @param  NewState: new state of the LSI.
  *   This parameter can be: ENABLE or DISABLE.
  * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
  *         clock cycles. 
  * @retval None
  */
void RCC_LSICmd(FunctionalState NewState)
{
  /* Check the parameters */
  assert_param(IS_FUNCTIONAL_STATE(NewState));
  
  *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;
}

/**
  * @brief  Configures the PLL clock source and multiplication factor.
  * @note   This function must be used only when the PLL is disabled.
  *   
  * @param  RCC_PLLSource: specifies the PLL entry clock source.
  *   This parameter can be one of the following values:
  *     @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock source
  *     @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock source
  * @note   The minimum input clock frequency for PLL is 2 MHz (when using HSE as
  *         PLL source).
  *               
  * @param  RCC_PLLMul: specifies the PLL multiplication factor, which drive the PLLVCO clock
  *   This parameter can be:
  *     @arg RCC_PLLMul_3: PLL clock source multiplied by 3
  *     @arg RCC_PLLMul_4: PLL clock source multiplied by 4
  *     @arg RCC_PLLMul_6: PLL clock source multiplied by 6
  *     @arg RCC_PLLMul_8: PLL clock source multiplied by 8
  *     @arg RCC_PLLMul_12: PLL clock source multiplied by 12
  *     @arg RCC_PLLMul_16: PLL clock source multiplied by 16  
  *     @arg RCC_PLLMul_24: PLL clock source multiplied by 24
  *     @arg RCC_PLLMul_32: PLL clock source multiplied by 32
  *     @arg RCC_PLLMul_48: PLL clock source multiplied by 48
  * @note   The application software must set correctly the PLL multiplication
  *         factor to avoid exceeding
  *             - 96 MHz as PLLVCO when the product is in range 1
  *             - 48 MHz as PLLVCO when the product is in range 2
  *             - 24 MHz when the product is in range 3
  * @note   When using the USB the PLLVCO should be 96MHz
  *                                   
  * @param  RCC_PLLDiv: specifies the PLL division factor.
  *   This parameter can be:
  *     @arg RCC_PLLDiv_2: PLL Clock output divided by 2  
  *     @arg RCC_PLLDiv_3: PLL Clock output divided by 3         
  *     @arg RCC_PLLDiv_4: PLL Clock output divided by 4  
  * @note   The application software must set correctly the output division to avoid
  *         exceeding 32 MHz as SYSCLK.
  *            
  * @retval None
  */
void RCC_PLLConfig(uint8_t RCC_PLLSource, uint8_t RCC_PLLMul, uint8_t RCC_PLLDiv)
{
  /* Check the parameters */
  assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
  assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
  assert_param(IS_RCC_PLL_DIV(RCC_PLLDiv));
  
  *(__IO uint8_t *) CFGR_BYTE3_ADDRESS = (uint8_t)(RCC_PLLSource | ((uint8_t)(RCC_PLLMul | (uint8_t)(RCC_PLLDiv))));
}

/**
  * @brief  Enables or disables the PLL.
  * @note   - After enabling the PLL, the application software should wait on 
  *           PLLRDY flag to be set indicating that PLL clock is stable and can
  *           be used as system clock source.
  *         - The PLL can not be disabled if it is used as system clock source
  *         - The PLL is disabled by hardware when entering STOP and STANDBY modes.    
  * @param  NewState: new state of the PLL.
  *   This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void RCC_PLLCmd(FunctionalState NewState)
{
  /* Check the parameters */
  assert_param(IS_FUNCTIONAL_STATE(NewState));
  
  *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;
}

/**
  * @brief  Enables or disables the Clock Security System.
  * @note   If a failure is detected on the HSE oscillator clock, this oscillator
  *         is automatically disabled and an interrupt is generated to inform the
  *         software about the failure (Clock Security System Interrupt, CSSI),
  *         allowing the MCU to perform rescue operations. The CSSI is linked to 
  *         the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector.  
  * @param  NewState: new state of the Clock Security System.
  *         This parameter can be: ENABLE or DISABLE.
  * @retval None
  */
void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
{
  /* Check the parameters */
  assert_param(IS_FUNCTIONAL_STATE(NewState));
  
  *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;
}

/**
  * @brief  Selects the clock source to output on MCO pin (PA8).
  * @note   PA8 should be configured in alternate function mode.   
  * @param  RCC_MCOSource: specifies the clock source to output.
  *   This parameter can be one of the following values:
  *     @arg RCC_MCOSource_NoClock: No clock selected
  *     @arg RCC_MCOSource_SYSCLK: System clock selected
  *     @arg RCC_MCOSource_HSI: HSI oscillator clock selected
  *     @arg RCC_MCOSource_MSI: MSI oscillator clock selected  
  *     @arg RCC_MCOSource_HSE: HSE oscillator clock selected
  *     @arg RCC_MCOSource_PLLCLK: PLL clock selected
  *     @arg RCC_MCOSource_LSI: LSI clock selected
  *     @arg RCC_MCOSource_LSE: LSE clock selected    
  * @param  RCC_MCODiv: specifies the MCO prescaler.
  *   This parameter can be one of the following values: 
  *     @arg RCC_MCODiv_1: no division applied to MCO clock 
  *     @arg RCC_MCODiv_2: division by 2 applied to MCO clock
  *     @arg RCC_MCODiv_4: division by 4 applied to MCO clock
  *     @arg RCC_MCODiv_8: division by 8 applied to MCO clock
  *     @arg RCC_MCODiv_16: division by 16 applied to MCO clock             
  * @retval None
  */
void RCC_MCOConfig(uint8_t RCC_MCOSource, uint8_t RCC_MCODiv)
{
  /* Check the parameters */
  assert_param(IS_RCC_MCO_SOURCE(RCC_MCOSource));
  assert_param(IS_RCC_MCO_DIV(RCC_MCODiv));
    
  /* Select MCO clock source and prescaler */
  *(__IO uint8_t *) CFGR_BYTE4_ADDRESS =  RCC_MCOSource | RCC_MCODiv; 
}

/**
  * @}
  */

/** @defgroup RCC_Group2 System AHB and APB busses clocks configuration functions
 *  @brief   System, AHB and APB busses clocks configuration functions
 *
@verbatim   
 ===============================================================================
             System, AHB and APB busses clocks configuration functions
 ===============================================================================  

  This section provide functions allowing to configure the System, AHB, APB1 and 
  APB2 busses clocks.
  
  1. Several clock sources can be used to drive the System clock (SYSCLK): MSI, HSI,
     HSE and PLL.
     The AHB clock (HCLK) is derived from System clock through configurable prescaler
     and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA and GPIO).
     APB1 (PCLK1) and APB2 (PCLK2) clocks are derived from AHB clock through 
     configurable prescalers and used to clock the peripherals mapped on these busses.
     You can use "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks.  

Note: All the peripheral clocks are derived from the System clock (SYSCLK) except:
====   - The USB 48 MHz clock which is derived from the PLL VCO clock.
       - The ADC clock which is always the HSI clock. A divider by 1, 2 or 4 allows
         to adapt the clock frequency to the device operating conditions. 
       - The RTC/LCD clock which is derived from the LSE, LSI or 1 MHz HSE_RTC (HSE
         divided by a programmable prescaler).
         The System clock (SYSCLK) frequency must be higher or equal to the RTC/LCD
         clock frequency.
       - IWDG clock which is always the LSI clock.
       
  2. The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 32 MHz.
     Depending on the device voltage range, the maximum frequency should be 
     adapted accordingly:
        +----------------------------------------------------------------+     
        |  Wait states  |                HCLK clock frequency (MHz)      |
        |               |------------------------------------------------|     
        |   (Latency)   |            voltage range       | voltage range |