wcdma_2ndinter_de.c

5个文件

/****************************************************************
 File Name: t3g_2ndinter_de.c
****************************************************************/
#include "c2f77defs.h"
#define IVER 1999
#define IREV 5

typedef float SIGNAL;

#include <stdlib.h>
#include <math.h>

#ifdef USE_PROTOS
void M5008_1008_2_t3g_2ndinter_de_9909(long *iparam, float *rparam)
#else
void M5008_1008_2_t3g_2ndinter_de_9909(iparam, rparam)
long *iparam;
float *rparam;
#endif
{
  long ccg_npast, ccg_nfut, ccg_istat, ccg_savearea = 0;
  long ccg_pos = 0, ccg_len = 0;

  long BlockFactor;

  /* port declarations */
  /* 1. inputport */
  int *Indata;
  /* 1. outport */
  int *Outdata;
  int *ccg_Outdata;
  long ccg_outrate_Outdata = 1;

  /* parameter declarations */
  /* 1. parameter */
  int InterlLength;
  /* 2. parameter */
  int InterMode;

  /* state declarations */
  int *datain, *ccg_datain;
  int *dataout, *ccg_dataout;
  int *P, *ccg_P;

#include "lclpar.h"
#include "scrtch.h"
#include "modsrc.h"

  /* get parameters */
  InterlLength = GetParameter_I(1);
  InterMode = GetParameter_I(2);

  switch (init)
  {
    case 1:
      SetVersion;
      SetRevision;

      /* map state datain to scratch area */
      ChkScratchPadSize( ccg_pos + (InterlLength) );
      ccg_len = InterlLength;
      datain = ccg_datain = &ih[ccg_pos];
      { int ccg_i = 0; for (;ccg_i < (InterlLength) ; ccg_i++) datain[ccg_i] = 0;}
      ccg_pos += ccg_len;

      /* map state dataout to scratch area */
      ChkScratchPadSize( ccg_pos + (InterlLength) );
      ccg_len = InterlLength;
      dataout = ccg_dataout = &ih[ccg_pos];
      { int ccg_i = 0; for (;ccg_i < (InterlLength) ; ccg_i++) dataout[ccg_i] = 0;}
      ccg_pos += ccg_len;

      /* map state P to scratch area */
      ChkScratchPadSize( ccg_pos + (30) );
      ccg_len = 30;
      P = ccg_P = &ih[ccg_pos];
      /* initialize state */
      P[0] = 0;
      P[1] = 20;
      P[2] = 10;
      P[3] = 5;
      P[4] = 15;
      P[5] = 25;
      P[6] = 3;
      P[7] = 13;
      P[8] = 23;
      P[9] = 8;
      P[10] = 18;
      P[11] = 28;
      P[12] = 1;
      P[13] = 11;
      P[14] = 21;
      P[15] = 6;
      P[16] = 16;
      P[17] = 26;
      P[18] = 4;
      P[19] = 14;
      P[20] = 24;
      P[21] = 19;
      P[22] = 9;
      P[23] = 29;
      P[24] = 12;
      P[25] = 2;
      P[26] = 7;
      P[27] = 22;
      P[28] = 27;
      P[29] = 17;
      /* check if initial values fit */
      if (30 > 30)
        ExitWithError(-501);
      ccg_pos += ccg_len;


      /* set scheduling rates */
      SetInputSchedule(1) =  InterlLength;

      /* save all states */
      ccg_savearea++;
      ccg_len = InterlLength;
      vsav(&mseqn, ccg_datain, &ccg_len, &ccg_savearea, &ccg_istat);
      ExitOnError(-ccg_istat);

      ccg_savearea++;
      ccg_len = InterlLength;
      vsav(&mseqn, ccg_dataout, &ccg_len, &ccg_savearea, &ccg_istat);
      ExitOnError(-ccg_istat);

      ccg_savearea++;
      ccg_len = 30;
      vsav(&mseqn, ccg_P, &ccg_len, &ccg_savearea, &ccg_istat);
      ExitOnError(-ccg_istat);



      return;

    case 2:
      /* get all states */
      ccg_savearea++;
      ChkScratchPadSize( ccg_pos + (InterlLength) );
      datain = ccg_datain = &ih[ccg_pos];
      vget(&mseqn, datain, &ccg_len, &ccg_savearea, &ccg_istat);
      ExitOnError(-ccg_istat);
      ccg_pos += ccg_len;

      ccg_savearea++;
      ChkScratchPadSize( ccg_pos + (InterlLength) );
      dataout = ccg_dataout = &ih[ccg_pos];
      vget(&mseqn, dataout, &ccg_len, &ccg_savearea, &ccg_istat);
      ExitOnError(-ccg_istat);
      ccg_pos += ccg_len;

      ccg_savearea++;
      ChkScratchPadSize( ccg_pos + (30) );
      P = ccg_P = &ih[ccg_pos];
      vget(&mseqn, P, &ccg_len, &ccg_savearea, &ccg_istat);
      ExitOnError(-ccg_istat);
      ccg_pos += ccg_len;


      /* ringbuffer check */
      rbchk( InPort(1), &ccg_npast, &ccg_nfut, &ccg_istat);
      ExitOnError(-ccg_istat);
      BlockFactor = ccg_nfut/( InterlLength);
      if ( BlockFactor < 1 )  return;


      /* get rates of output ports */
      ccg_outrate_Outdata = GetOutputRate(1);
      if ( ( InterlLength)*BlockFactor > ccg_outrate_Outdata )
        BlockFactor = ccg_outrate_Outdata/( InterlLength);
      if ( BlockFactor < 1 ) BlockFactor = 1;


      /* read input signals */
      ccg_len = ( InterlLength)*BlockFactor;
      ChkScratchPadSize(ccg_pos+ccg_len);
      Indata = &ih[ccg_pos];
      rbrd( InPort(1), Indata, &ccg_len, &ccg_istat);
      ExitOnError(-ccg_istat);
      ccg_pos += ccg_len;


      /* prepare scratch area for output signals */
      ccg_len = ( InterlLength)*BlockFactor;
      ChkScratchPadSize(ccg_pos+ccg_len);
      Outdata = ccg_Outdata = &ih[ccg_pos];
      ccg_pos += ccg_len;


      /* signal processing code */
      {
          register long ccg_lp0;

           int i,j,k;
          int R2;
          int temp;
          

           
         for(ccg_lp0=BlockFactor; ccg_lp0-- > 0;) {

          for (i = 0; i < InterlLength; i++) { datain[i] = *Indata++; }
          
          R2 = floor((double)(InterlLength/30));
          if (InterlLength%30 != 0)  { R2 = R2 + 1;  }
          
           
          switch (InterMode) 
          {
           case 1:
            
            for (i = 0;i < 30;++i)
             {
              for (j = 0;j < R2;++j) 
               {
                 temp = j * 30 + P[i];
                 if (temp < InterlLength)
                   { *Outdata++ = datain[temp];}
               }
             }
            
            break;
            
          case -1:
          
           k = 0;
           for (i = 0;i < 30;++i)
             {
              for (j = 0;j < R2;++j) 
               {
                 temp = j * 30 + P[i];
                 if (temp < InterlLength)
                   { dataout[temp] = datain[k]; ++k;}
               }
             }
             
            for (i = 0; i < InterlLength; i++) { *Outdata++ = dataout[i]; }
          
            break;
           
          default:
          
               break;    
               
          } 
         }  

         

      }

      /* write output signals */
      ccg_len = ( InterlLength) * BlockFactor;
      rbwr(OutPort(1),ccg_Outdata, &ccg_len, &ccg_istat);
      ExitOnError(-ccg_istat);

      /* initialize save area index */
      ccg_savearea = 0;
      /* save all states */
      ccg_savearea++;
      ccg_len = InterlLength;
      vsav(&mseqn, ccg_datain, &ccg_len, &ccg_savearea, &ccg_istat);
      ExitOnError(-ccg_istat);

      ccg_savearea++;
      ccg_len = InterlLength;
      vsav(&mseqn, ccg_dataout, &ccg_len, &ccg_savearea, &ccg_istat);
      ExitOnError(-ccg_istat);

      ccg_savearea++;
      ccg_len = 30;
      vsav(&mseqn, ccg_P, &ccg_len, &ccg_savearea, &ccg_istat);
      ExitOnError(-ccg_istat);



      return;

    case 3:

      return;
  }
}