wcdma_1stinterleaver.c

5个文件

/****************************************************************
 File Name: t3g_1stinterleaver.c
****************************************************************/
#include "c2f77defs.h"
#define IVER 1999
#define IREV 5

typedef float SIGNAL;

#include "stdlib.h"

#ifdef USE_PROTOS
void M5008_1008_2_t3g_1stinterleaver_9909(long *iparam, float *rparam)
#else
void M5008_1008_2_t3g_1stinterleaver_9909(iparam, rparam)
long *iparam;
float *rparam;
#endif
{
  long ccg_npast, ccg_nfut, ccg_istat, ccg_savearea = 0;
  long ccg_pos = 0, ccg_len = 0;

  long BlockFactor;

  /* port declarations */
  /* 1. inputport */
  long *DataBefInterl;
  /* 1. outport */
  long *DataAftInterl;
  long *ccg_DataAftInterl;
  long ccg_outrate_DataAftInterl = 1;

  /* parameter declarations */
  /* 1. parameter */
  long NumBlock;
  /* 2. parameter */
  long InterlLength;

  /* state declarations */
  long *data, *ccg_data;

#include "lclpar.h"
#include "scrtch.h"
#include "modsrc.h"

  /* get parameters */
  NumBlock = GetParameter_I(1);
  InterlLength = GetParameter_I(2);

  switch (init)
  {
    case 1:
      SetVersion;
      SetRevision;

      /* map state data to scratch area */
      ChkScratchPadSize( ccg_pos + (InterlLength) );
      ccg_len = InterlLength;
      data = ccg_data = &ih[ccg_pos];
      { int ccg_i = 0; for (;ccg_i < (InterlLength) ; ccg_i++) data[ccg_i] = 0;}
      ccg_pos += ccg_len;


      /* set scheduling rates */
      SetInputSchedule(1) =  InterlLength;

      /* save all states */
      ccg_savearea++;
      ccg_len = InterlLength;
      vsav(&mseqn, ccg_data, &ccg_len, &ccg_savearea, &ccg_istat);
      ExitOnError(-ccg_istat);



      return;

    case 2:
      /* get all states */
      ccg_savearea++;
      ChkScratchPadSize( ccg_pos + (InterlLength) );
      data = ccg_data = &ih[ccg_pos];
      vget(&mseqn, data, &ccg_len, &ccg_savearea, &ccg_istat);
      ExitOnError(-ccg_istat);
      ccg_pos += ccg_len;


      /* ringbuffer check */
      rbchk( InPort(1), &ccg_npast, &ccg_nfut, &ccg_istat);
      ExitOnError(-ccg_istat);
      BlockFactor = ccg_nfut/( InterlLength);
      if ( BlockFactor < 1 )  return;


      /* get rates of output ports */
      ccg_outrate_DataAftInterl = GetOutputRate(1);
      if ( ( InterlLength)*BlockFactor > ccg_outrate_DataAftInterl )
        BlockFactor = ccg_outrate_DataAftInterl/( InterlLength);
      if ( BlockFactor < 1 ) BlockFactor = 1;


      /* read input signals */
      ccg_len = ( InterlLength)*BlockFactor;
      ChkScratchPadSize(ccg_pos+ccg_len);
      DataBefInterl = &ih[ccg_pos];
      rbrd( InPort(1), DataBefInterl, &ccg_len, &ccg_istat);
      ExitOnError(-ccg_istat);
      ccg_pos += ccg_len;


      /* prepare scratch area for output signals */
      ccg_len = ( InterlLength)*BlockFactor;
      ChkScratchPadSize(ccg_pos+ccg_len);
      DataAftInterl = ccg_DataAftInterl = &ih[ccg_pos];
      ccg_pos += ccg_len;


      /* signal processing code */
      {
          register long ccg_lp0;

         for(ccg_lp0=BlockFactor; ccg_lp0-- > 0;) {
          
          register long i;
           
           for (i = 0; i < InterlLength; i++) { data[i] = *DataBefInterl++; }
              
           switch(NumBlock)
             {
              case 1:
                     for (i = 0; i < InterlLength; i++) { *DataAftInterl++ = data[i]; }
                     break;
              case 2:
                     for (i = 0; i < InterlLength; i+=2) { *DataAftInterl++ = data[i]; }
         	     for (i = 1; i < InterlLength; i+=2) { *DataAftInterl++ = data[i]; }
                     break;
              case 4:
                     for (i = 0; i < InterlLength; i+=4) { *DataAftInterl++ = data[i]; }
                     for (i = 2; i < InterlLength; i+=4) { *DataAftInterl++ = data[i]; }
                     for (i = 1; i < InterlLength; i+=4) { *DataAftInterl++ = data[i]; }
                     for (i = 3; i < InterlLength; i+=4) { *DataAftInterl++ = data[i]; }
                     break;
              case 8:
                     for (i = 0; i < InterlLength; i+=8) { *DataAftInterl++ = data[i]; }
                     for (i = 4; i < InterlLength; i+=8) { *DataAftInterl++ = data[i]; }
                     for (i = 2; i < InterlLength; i+=8) { *DataAftInterl++ = data[i]; }
                     for (i = 6; i < InterlLength; i+=8) { *DataAftInterl++ = data[i]; }
                     for (i = 1; i < InterlLength; i+=8) { *DataAftInterl++ = data[i]; }
                     for (i = 5; i < InterlLength; i+=8) { *DataAftInterl++ = data[i]; }
                     for (i = 3; i < InterlLength; i+=8) { *DataAftInterl++ = data[i]; }
                     for (i = 7; i < InterlLength; i+=8) { *DataAftInterl++ = data[i]; }
                     break;
             }
                     
          
         }

      }

      /* write output signals */
      ccg_len = ( InterlLength) * BlockFactor;
      rbwr(OutPort(1),ccg_DataAftInterl, &ccg_len, &ccg_istat);
      ExitOnError(-ccg_istat);

      /* initialize save area index */
      ccg_savearea = 0;
      /* save all states */
      ccg_savearea++;
      ccg_len = InterlLength;
      vsav(&mseqn, ccg_data, &ccg_len, &ccg_savearea, &ccg_istat);
      ExitOnError(-ccg_istat);



      return;

    case 3:

      return;
  }
}