📄 wcdma_1stinter_de.c
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/****************************************************************
File Name: t3g_1stinter_de.c
****************************************************************/
#include "c2f77defs.h"
#define IVER 1999
#define IREV 5
typedef float SIGNAL;
#include "stdlib.h"
#ifdef USE_PROTOS
void M5008_1008_2_t3g_1stinter_de_9909(long *iparam, float *rparam)
#else
void M5008_1008_2_t3g_1stinter_de_9909(iparam, rparam)
long *iparam;
float *rparam;
#endif
{
long ccg_npast, ccg_nfut, ccg_istat, ccg_savearea = 0;
long ccg_pos = 0, ccg_len = 0;
long BlockFactor;
/* port declarations */
/* 1. inputport */
int *DataBefInterl;
/* 1. outport */
int *DataAftInterl;
int *ccg_DataAftInterl;
long ccg_outrate_DataAftInterl = 1;
/* parameter declarations */
/* 1. parameter */
int TTI;
/* 2. parameter */
int InterMode;
/* 3. parameter */
int InterlLength;
/* state declarations */
int *data, *ccg_data;
#include "lclpar.h"
#include "scrtch.h"
#include "modsrc.h"
/* get parameters */
TTI = GetParameter_I(1);
InterMode = GetParameter_I(2);
InterlLength = GetParameter_I(3);
switch (init)
{
case 1:
SetVersion;
SetRevision;
/* map state data to scratch area */
ChkScratchPadSize( ccg_pos + (InterlLength) );
ccg_len = InterlLength;
data = ccg_data = &ih[ccg_pos];
{ int ccg_i = 0; for (;ccg_i < (InterlLength) ; ccg_i++) data[ccg_i] = 0;}
ccg_pos += ccg_len;
/* set scheduling rates */
SetInputSchedule(1) = InterlLength;
/* save all states */
ccg_savearea++;
ccg_len = InterlLength;
vsav(&mseqn, ccg_data, &ccg_len, &ccg_savearea, &ccg_istat);
ExitOnError(-ccg_istat);
return;
case 2:
/* get all states */
ccg_savearea++;
ChkScratchPadSize( ccg_pos + (InterlLength) );
data = ccg_data = &ih[ccg_pos];
vget(&mseqn, data, &ccg_len, &ccg_savearea, &ccg_istat);
ExitOnError(-ccg_istat);
ccg_pos += ccg_len;
/* ringbuffer check */
rbchk( InPort(1), &ccg_npast, &ccg_nfut, &ccg_istat);
ExitOnError(-ccg_istat);
BlockFactor = ccg_nfut/( InterlLength);
if ( BlockFactor < 1 ) return;
/* get rates of output ports */
ccg_outrate_DataAftInterl = GetOutputRate(1);
if ( ( InterlLength)*BlockFactor > ccg_outrate_DataAftInterl )
BlockFactor = ccg_outrate_DataAftInterl/( InterlLength);
if ( BlockFactor < 1 ) BlockFactor = 1;
/* read input signals */
ccg_len = ( InterlLength)*BlockFactor;
ChkScratchPadSize(ccg_pos+ccg_len);
DataBefInterl = &ih[ccg_pos];
rbrd( InPort(1), DataBefInterl, &ccg_len, &ccg_istat);
ExitOnError(-ccg_istat);
ccg_pos += ccg_len;
/* prepare scratch area for output signals */
ccg_len = ( InterlLength)*BlockFactor;
ChkScratchPadSize(ccg_pos+ccg_len);
DataAftInterl = ccg_DataAftInterl = &ih[ccg_pos];
ccg_pos += ccg_len;
/* signal processing code */
{
register long ccg_lp0;
int i,j;
int temp;
int R1;
int P4[4] = {0,2,1,3};
int P8[8] = {0,4,2,6,1,5,3,7};
for(ccg_lp0=BlockFactor; ccg_lp0-- > 0;) {
for (i = 0; i < InterlLength; i++) { data[i] = *DataBefInterl++; }
switch(InterMode)
{
case 1:
{
switch(TTI)
{
case 10:
for (i = 0; i < InterlLength; i++) { *DataAftInterl++ = data[i]; }
break;
case 20:
R1 = InterlLength/2;
for (i = 0; i < 2; ++i )
{
for (j = 0; j < R1; ++j)
{
temp = 2 * j + i;
*DataAftInterl++ = data[temp];
}
}
break;
case 40:
R1 = InterlLength/4;
for (i = 0; i < 4; ++i )
{
for (j = 0; j < R1; ++j)
{
temp = 4 * j + P4[i];
*DataAftInterl++ = data[temp];
}
}
break;
case 80:
R1 = InterlLength/8;
for (i = 0; i < 8; ++i )
{
for (j = 0; j < R1; ++j)
{
temp = 8 * j + P8[i];
*DataAftInterl++ = data[temp];
}
}
break;
default:
break;
} /* endof 2switch */
break;
} /* endof case 1 */
case -1:
{
switch(TTI)
{
case 10:
for (i = 0; i < InterlLength; i++) { *DataAftInterl++ = data[i]; }
break;
case 20:
R1 = InterlLength/2;
for (i = 0; i < R1; ++i )
{
for (j = 0; j < 2; ++j)
{
temp = j * R1 + i;
*DataAftInterl++ = data[temp];
}
}
break;
case 40:
R1 = InterlLength/4;
for (i = 0; i < R1; ++i )
{
for (j = 0; j < 4; ++j)
{
temp = R1 * P4[j] + i;
*DataAftInterl++ = data[temp];
}
}
break;
case 80:
R1 = InterlLength/8;
for (i = 0; i < R1; ++i )
{
for (j = 0; j < 8; ++j)
{
temp = R1 * P8[j] + i;
*DataAftInterl++ = data[temp];
}
}
break;
default:
break;
} /* endof 3switch */
break;
} /* endof case -1 */
default:
break;
} /* endof 1switch */
}
}
/* write output signals */
ccg_len = ( InterlLength) * BlockFactor;
rbwr(OutPort(1),ccg_DataAftInterl, &ccg_len, &ccg_istat);
ExitOnError(-ccg_istat);
/* initialize save area index */
ccg_savearea = 0;
/* save all states */
ccg_savearea++;
ccg_len = InterlLength;
vsav(&mseqn, ccg_data, &ccg_len, &ccg_savearea, &ccg_istat);
ExitOnError(-ccg_istat);
return;
case 3:
return;
}
}
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