pid.h

UCSO在三星S3C44B0X CPU上的移植。ｅｊｏｙ ｉｔ

/*
 * File:	pid.h
 *
 * uC/OS Real-time multitasking kernel for the ARM processor.
 *
 * PID board includes. 
 * Created by Marco Graziano ([e-mail]).
 *
 */

#define IOBASE		0x02000000		/* I/O space start address */

#define INTCREGS        (IOBASE)
#define	UARTREGS	(IOBASE + 0x20)
#define	PARPREGS	(IOBASE + 0x60)

#define MAXIRQNUM       7
#define MAXFIQNUM       7
#define MAXSWINUM       31

#define	RESETV		0
#define	UNDV		1
#define	SWIV		2
#define	IABTV		3
#define	DABTV		4
#define	IRQV		6
#define	FIQV		7

#define	SerialIRQNum	0
#define	TimerIRQNum	1
#define PanicIRQNum	7

/* Structure to map INTC registers */
struct INTC {
        union {
                ureg Status;
                ureg Reset;
	} IRQ; 
        ureg    IRQMask;
        ureg    FIQStatus;
        ureg    FIQMask;
};

/* Structure to map 16C551 parallel port registers */
struct PARP {
        ureg    DRW;            /* data read write register */
        ureg    PSR;            /* port status register */
        ureg    PCR;            /* port control register */
        ureg    GPR;            /* general purpose register */
};

/* Structure to map 16C551 UART registers */
struct UART {
        union {
                ureg    RBR;    /* receive buffer register (R/O) */
                ureg    THR;    /* transmitter holding register (W/O) */
                ureg    DLL;    /* lsb divisor latch (R/W) */
        } Reg1;
        union {
                ureg    IER;    /* interrupt enable register (R/W) */
                ureg    DLM;    /* msb divisor latch (R/W) */
        } Reg2;
        union {
                ureg    IIR;    /* interrupt identification register (R/O) */
                ureg    FCR;    /* FIFO control register (W/O) */
        } Reg3;
        ureg    LCR;            /* line control register (R/W) */
        ureg    MCR;            /* modem control register (R/W) */
        ureg    LSR;            /* line status register (R/W) */
        ureg    MSR;            /* modem status register (R/W) */
        ureg    SCR;            /* scratch register (R/W) */
};

 
/* 
 * MMU data structures and constants 
 */
 
/* First level page table entry */
struct LevelOne {
        uint    Type:2;
        uint    Bufferable:1;
        uint    Cacheable:1;
        uint    Updateable:1;
        uint    Domain:4;
        uint    :1;
        uint    AccessPermission:2;
        uint    :8;
        uint    BaseAddress:12;
};       
 
/* Access Permission bits */
#define NOPERM  0x0             /* any access generates a permission fault */
#define SVPERM  0x1             /* access allowed only in supervisor mode */
#define RDONLY  0x2             /* write in user mode causes permission fault */
#define RDWR    0x3             /* all access permitted */
 
/* Level one descriptor types */
#define INVALID 0x0
#define PAGE    0x1
#define SECTION 0x2

/*
 * Functions specific to the PID board
 */

/* defined in pid.c */
extern void    PIDInit(void);          
extern void    IRQEnable(int);
extern void    IRQDisable(int);
extern void    IRQReset(int);
extern PFV     IRQInstall(int, PFV);
extern void    FIQEnable(int);
extern void    FIQDisable(int);
extern PFV     FIQInstall(int, PFV);
extern PFV     SWIInstall(int, PFV);
extern void    PutByte(byte);
extern byte    GetByte(void);
extern void    SetLED(uint);

/* defined in subr.s */
extern  PFV NewIRQ(PFI);        
extern  PFV NewFIQ(PFV);
extern  PFV NewSWI(PFV);