sa1110.h

UCOS在CS8900上面移植代码

//------------------------------------------------------------------------------
// 颇 老 疙 : sa1110.h
// 橇肺璃飘 : ezboot
// 汲    疙 : ezboot俊辑 荤侩窍绰 sa1110俊 包访等 郴侩
// 累 己 磊 : 蜡康芒
// 累 己 老 : 2001斥 11岿 3老
// 荐 沥 老 : 
// 林    狼 : 捞 庆歹 拳老狼 措何盒狼 郴侩篮 
//            ARM Linux狼 庆歹 拳老 linux/include/asm-arm\arch-sa1100
//            俊辑 啊廉 吭促. 
//------------------------------------------------------------------------------

#ifndef _SA1110_HEADER_
#define _SA1110_HEADER_

//-----------------------------------------------------------------------------
//
// 扁夯 屈俊 措茄 沥狼  
//
//-----------------------------------------------------------------------------
typedef unsigned char   Byte;
typedef unsigned short  Word16 ;
typedef unsigned int    Word32 ;
typedef Word32          Word ;
typedef Word            Quad [4] ;
typedef void            *Address ;
typedef void            (*ExcpHndlr) (void) ;


//-----------------------------------------------------------------------------
//
// 扁夯 单捞鸥 贸府 概农肺 
//
//-----------------------------------------------------------------------------
#define UData(Data)	((unsigned int) (Data))

#define Fld(Size, Shft)	(((Size) << 16) + (Shft))

#define FSize(Field)	((Field) >> 16)
#define FShft(Field)	((Field) & 0x0000FFFF)
#define FMsk(Field)	(((UData (1) << FSize (Field)) - 1) << FShft (Field))
#define FAlnMsk(Field)	((UData (1) << FSize (Field)) - 1)
#define F1stBit(Field)	(UData (1) << FShft (Field))

#define io_p2v(PhAdd)	(PhAdd)


//-----------------------------------------------------------------------------
//
// UART 3 
//
//-----------------------------------------------------------------------------

#define _UTCR0(Nb)	        	/* UART Control Reg. 0 [1..3]      */ \
                	(0x80010000 + ((Nb) - 1)*0x00020000)
#define _UTCR1(Nb)	        	/* UART Control Reg. 1 [1..3]      */ \
                	(0x80010004 + ((Nb) - 1)*0x00020000)
#define _UTCR2(Nb)	        	/* UART Control Reg. 2 [1..3]      */ \
                	(0x80010008 + ((Nb) - 1)*0x00020000)
#define _UTCR3(Nb)	        	/* UART Control Reg. 3 [1..3]      */ \
                	(0x8001000C + ((Nb) - 1)*0x00020000)
#define _UTCR4(Nb)	        	/* UART Control Reg. 4 [2]         */ \
                	(0x80010010 + ((Nb) - 1)*0x00020000)
#define _UTDR(Nb)	        	/* UART Data Reg. [1..3]           */ \
                	(0x80010014 + ((Nb) - 1)*0x00020000)
#define _UTSR0(Nb)	        	/* UART Status Reg. 0 [1..3]       */ \
                	(0x8001001C + ((Nb) - 1)*0x00020000)
#define _UTSR1(Nb)	        	/* UART Status Reg. 1 [1..3]       */ \
                	(0x80010020 + ((Nb) - 1)*0x00020000)

#define _Ser3UTCR0	_UTCR0 (3)	/* Ser. port 3 UART Control Reg. 0 */
#define _Ser3UTCR1	_UTCR1 (3)	/* Ser. port 3 UART Control Reg. 1 */
#define _Ser3UTCR2	_UTCR2 (3)	/* Ser. port 3 UART Control Reg. 2 */
#define _Ser3UTCR3	_UTCR3 (3)	/* Ser. port 3 UART Control Reg. 3 */
#define _Ser3UTDR	_UTDR (3)	/* Ser. port 3 UART Data Reg.      */
#define _Ser3UTSR0	_UTSR0 (3)	/* Ser. port 3 UART Status Reg. 0  */
#define _Ser3UTSR1	_UTSR1 (3)	/* Ser. port 3 UART Status Reg. 1  */



#define UTCR0_PE	0x00000001	/* Parity Enable                   */
#define UTCR0_OES	0x00000002	/* Odd/Even parity Select          */
#define UTCR0_OddPar	(UTCR0_OES*0)	/*  Odd Parity                     */
#define UTCR0_EvenPar	(UTCR0_OES*1)	/*  Even Parity                    */
#define UTCR0_SBS	0x00000004	/* Stop Bit Select                 */
#define UTCR0_1StpBit	(UTCR0_SBS*0)	/*  1 Stop Bit per frame           */
#define UTCR0_2StpBit	(UTCR0_SBS*1)	/*  2 Stop Bits per frame          */
#define UTCR0_DSS	0x00000008	/* Data Size Select                */
#define UTCR0_7BitData	(UTCR0_DSS*0)	/*  7-Bit Data                     */
#define UTCR0_8BitData	(UTCR0_DSS*1)	/*  8-Bit Data                     */
#define UTCR0_SCE	0x00000010	/* Sample Clock Enable             */
                	        	/* (ser. port 1: GPIO [18],        */
                	        	/* ser. port 3: GPIO [20])         */
#define UTCR0_RCE	0x00000020	/* Receive Clock Edge select       */
#define UTCR0_RcRsEdg	(UTCR0_RCE*0)	/*  Receive clock Rising-Edge      */
#define UTCR0_RcFlEdg	(UTCR0_RCE*1)	/*  Receive clock Falling-Edge     */
#define UTCR0_TCE	0x00000040	/* Transmit Clock Edge select      */
#define UTCR0_TrRsEdg	(UTCR0_TCE*0)	/*  Transmit clock Rising-Edge     */
#define UTCR0_TrFlEdg	(UTCR0_TCE*1)	/*  Transmit clock Falling-Edge    */

#define UTCR1_BRD	Fld (4, 0)	/* Baud Rate Divisor/16 - 1 [11:8] */
#define UTCR2_BRD	Fld (8, 0)	/* Baud Rate Divisor/16 - 1  [7:0] */
                	        	/* fua = fxtl/(16*(BRD[11:0] + 1)) */
                	        	/* Tua = 16*(BRD [11:0] + 1)*Txtl  */
#define UTCR1_BdRtDiv(Div)      	/*  Baud Rate Divisor [16..65536]  */ \
                	(((Div) - 16)/16 >> FSize (UTCR2_BRD) << \
                	 FShft (UTCR1_BRD))
#define UTCR2_BdRtDiv(Div)      	/*  Baud Rate Divisor [16..65536]  */ \
                	(((Div) - 16)/16 & FAlnMsk (UTCR2_BRD) << \
                	 FShft (UTCR2_BRD))
                	        	/*  fua = fxtl/(16*Floor (Div/16)) */
                	        	/*  Tua = 16*Floor (Div/16)*Txtl   */
#define UTCR1_CeilBdRtDiv(Div)  	/*  Ceil. of BdRtDiv [16..65536]   */ \
                	(((Div) - 1)/16 >> FSize (UTCR2_BRD) << \
                	 FShft (UTCR1_BRD))
#define UTCR2_CeilBdRtDiv(Div)  	/*  Ceil. of BdRtDiv [16..65536]   */ \
                	(((Div) - 1)/16 & FAlnMsk (UTCR2_BRD) << \
                	 FShft (UTCR2_BRD))
                	        	/*  fua = fxtl/(16*Ceil (Div/16))  */
                	        	/*  Tua = 16*Ceil (Div/16)*Txtl    */

#define UTCR3_RXE	0x00000001	/* Receive Enable                  */
#define UTCR3_TXE	0x00000002	/* Transmit Enable                 */
#define UTCR3_BRK	0x00000004	/* BReaK mode                      */
#define UTCR3_RIE	0x00000008	/* Receive FIFO 1/3-to-2/3-full or */
                	        	/* more Interrupt Enable           */
#define UTCR3_TIE	0x00000010	/* Transmit FIFO 1/2-full or less  */
                	        	/* Interrupt Enable                */
#define UTCR3_LBM	0x00000020	/* Look-Back Mode                  */

#define UTDR_DATA	Fld (8, 0)	/* receive/transmit DATA FIFOs     */
#if 0           	        	/* Hidden receive FIFO bits        */
#define UTDR_PRE	0x00000100	/*  receive PaRity Error (read)    */
#define UTDR_FRE	0x00000200	/*  receive FRaming Error (read)   */
#define UTDR_ROR	0x00000400	/*  Receive FIFO Over-Run (read)   */
#endif /* 0 */

#define UTSR0_TFS	0x00000001	/* Transmit FIFO 1/2-full or less  */
                	        	/* Service request (read)          */
#define UTSR0_RFS	0x00000002	/* Receive FIFO 1/3-to-2/3-full or */
                	        	/* more Service request (read)     */
#define UTSR0_RID	0x00000004	/* Receiver IDle                   */
#define UTSR0_RBB	0x00000008	/* Receive Beginning of Break      */
#define UTSR0_REB	0x00000010	/* Receive End of Break            */
#define UTSR0_EIF	0x00000020	/* Error In FIFO (read)            */

#define UTSR1_TBY	0x00000001	/* Transmitter BusY (read)         */
#define UTSR1_RNE	0x00000002	/* Receive FIFO Not Empty (read)   */
#define UTSR1_TNF	0x00000004	/* Transmit FIFO Not Full (read)   */
#define UTSR1_PRE	0x00000008	/* receive PaRity Error (read)     */
#define UTSR1_FRE	0x00000010	/* receive FRaming Error (read)    */
#define UTSR1_ROR	0x00000020	/* Receive FIFO Over-Run (read)    */

//-----------------------------------------------------------------------------
//
// 鸥捞赣 
//
//-----------------------------------------------------------------------------
#define _OSMR(Nb)	        	/* OS timer Match Reg. [0..3]      */ \
                	(0x90000000 + (Nb)*4)
#define _OSMR0  	_OSMR (0)	/* OS timer Match Reg. 0           */
#define _OSMR1  	_OSMR (1)	/* OS timer Match Reg. 1           */
#define _OSMR2  	_OSMR (2)	/* OS timer Match Reg. 2           */
#define _OSMR3  	_OSMR (3)	/* OS timer Match Reg. 3           */
#define _OSCR   	0x90000010	/* OS timer Counter Reg.           */
#define _OSSR   	0x90000014	/* OS timer Status Reg.            */
#define _OWER   	0x90000018	/* OS timer Watch-dog Enable Reg.  */
#define _OIER   	0x9000001C	/* OS timer Interrupt Enable Reg.  */

#define OSMR    	        	/* OS timer Match Reg. [0..3]      */ \
                	((volatile Word *) io_p2v (_OSMR (0)))
#define OSMR0   	(OSMR [0])	/* OS timer Match Reg. 0           */
#define OSMR1   	(OSMR [1])	/* OS timer Match Reg. 1           */
#define OSMR2   	(OSMR [2])	/* OS timer Match Reg. 2           */
#define OSMR3   	(OSMR [3])	/* OS timer Match Reg. 3           */
#define OSCR    	        	/* OS timer Counter Reg.           */ \
                	(*((volatile Word *) io_p2v (_OSCR)))
#define OSSR    	        	/* OS timer Status Reg.            */ \
                	(*((volatile Word *) io_p2v (_OSSR)))
#define OWER    	        	/* OS timer Watch-dog Enable Reg.  */ \
                	(*((volatile Word *) io_p2v (_OWER)))
#define OIER    	        	/* OS timer Interrupt Enable Reg.  */ \
                	(*((volatile Word *) io_p2v (_OIER)))

#define OSSR_M(Nb)	        	/* Match detected [0..3]           */ \
                	(0x00000001 << (Nb))
#define OSSR_M0 	OSSR_M (0)	/* Match detected 0                */
#define OSSR_M1 	OSSR_M (1)	/* Match detected 1                */
#define OSSR_M2 	OSSR_M (2)	/* Match detected 2                */
#define OSSR_M3 	OSSR_M (3)	/* Match detected 3                */

#define OWER_WME	0x00000001	/* Watch-dog Match Enable          */
                	        	/* (set only)                      */

#define OIER_E(Nb)	        	/* match interrupt Enable [0..3]   */ \
                	(0x00000001 << (Nb))
#define OIER_E0 	OIER_E (0)	/* match interrupt Enable 0        */
#define OIER_E1 	OIER_E (1)	/* match interrupt Enable 1        */
#define OIER_E2 	OIER_E (2)	/* match interrupt Enable 2        */
#define OIER_E3 	OIER_E (3)	/* match interrupt Enable 3        */

//-----------------------------------------------------------------------------
//
// GPIO
//
//-----------------------------------------------------------------------------
#define _GPLR   	0x90040000	/* GPIO Pin Level Reg.             */
#define _GPDR   	0x90040004	/* GPIO Pin Direction Reg.         */
#define _GPSR   	0x90040008	/* GPIO Pin output Set Reg.        */
#define _GPCR   	0x9004000C	/* GPIO Pin output Clear Reg.      */
#define _GRER   	0x90040010	/* GPIO Rising-Edge detect Reg.    */
#define _GFER   	0x90040014	/* GPIO Falling-Edge detect Reg.   */
#define _GEDR   	0x90040018	/* GPIO Edge Detect status Reg.    */
#define _GAFR   	0x9004001C	/* GPIO Alternate Function Reg.    */

#define GPLR    	        	/* GPIO Pin Level Reg.             */ \
                	(*((volatile Word *) io_p2v (_GPLR)))
#define GPDR    	        	/* GPIO Pin Direction Reg.         */ \
                	(*((volatile Word *) io_p2v (_GPDR)))
#define GPSR    	        	/* GPIO Pin output Set Reg.        */ \
                	(*((volatile Word *) io_p2v (_GPSR)))
#define GPCR    	        	/* GPIO Pin output Clear Reg.      */ \
                	(*((volatile Word *) io_p2v (_GPCR)))
#define GRER    	        	/* GPIO Rising-Edge detect Reg.    */ \
                	(*((volatile Word *) io_p2v (_GRER)))
#define GFER    	        	/* GPIO Falling-Edge detect Reg.   */ \
                	(*((volatile Word *) io_p2v (_GFER)))
#define GEDR    	        	/* GPIO Edge Detect status Reg.    */ \
                	(*((volatile Word *) io_p2v (_GEDR)))
#define GAFR    	        	/* GPIO Alternate Function Reg.    */ \
                	(*((volatile Word *) io_p2v (_GAFR)))

#define GPIO_MIN	(0)
#define GPIO_MAX	(27)

#define GPIO_GPIO(Nb)	        	/* GPIO [0..27]                    */ \
                	(0x00000001 << (Nb))
#define GPIO_GPIO0	GPIO_GPIO (0)	/* GPIO  [0]                       */
#define GPIO_GPIO1	GPIO_GPIO (1)	/* GPIO  [1]                       */
#define GPIO_GPIO2	GPIO_GPIO (2)	/* GPIO  [2]                       */
#define GPIO_GPIO3	GPIO_GPIO (3)	/* GPIO  [3]                       */
#define GPIO_GPIO4	GPIO_GPIO (4)	/* GPIO  [4]                       */
#define GPIO_GPIO5	GPIO_GPIO (5)	/* GPIO  [5]                       */
#define GPIO_GPIO6	GPIO_GPIO (6)	/* GPIO  [6]                       */
#define GPIO_GPIO7	GPIO_GPIO (7)	/* GPIO  [7]                       */
#define GPIO_GPIO8	GPIO_GPIO (8)	/* GPIO  [8]                       */
#define GPIO_GPIO9	GPIO_GPIO (9)	/* GPIO  [9]                       */
#define GPIO_GPIO10	GPIO_GPIO (10)	/* GPIO [10]                       */
#define GPIO_GPIO11	GPIO_GPIO (11)	/* GPIO [11]                       */
#define GPIO_GPIO12	GPIO_GPIO (12)	/* GPIO [12]                       */
#define GPIO_GPIO13	GPIO_GPIO (13)	/* GPIO [13]                       */
#define GPIO_GPIO14	GPIO_GPIO (14)	/* GPIO [14]                       */
#define GPIO_GPIO15	GPIO_GPIO (15)	/* GPIO [15]                       */
#define GPIO_GPIO16	GPIO_GPIO (16)	/* GPIO [16]                       */
#define GPIO_GPIO17	GPIO_GPIO (17)	/* GPIO [17]                       */
#define GPIO_GPIO18	GPIO_GPIO (18)	/* GPIO [18]                       */
#define GPIO_GPIO19	GPIO_GPIO (19)	/* GPIO [19]                       */
#define GPIO_GPIO20	GPIO_GPIO (20)	/* GPIO [20]                       */
#define GPIO_GPIO21	GPIO_GPIO (21)	/* GPIO [21]                       */
#define GPIO_GPIO22	GPIO_GPIO (22)	/* GPIO [22]                       */
#define GPIO_GPIO23	GPIO_GPIO (23)	/* GPIO [23]                       */
#define GPIO_GPIO24	GPIO_GPIO (24)	/* GPIO [24]                       */
#define GPIO_GPIO25	GPIO_GPIO (25)	/* GPIO [25]                       */
#define GPIO_GPIO26	GPIO_GPIO (26)	/* GPIO [26]                       */
#define GPIO_GPIO27	GPIO_GPIO (27)	/* GPIO [27]                       */


//-----------------------------------------------------------------------------
//
// RESET CONTROLLER
//
//-----------------------------------------------------------------------------

#define _RSRR   	0x90030000	/* RC Software Reset Reg.          */
#define _RCSR   	0x90030004	/* RC Status Reg.                  */

#define RSRR    	        	/* RC Software Reset Reg.          */ \
                	(*((volatile Word *) io_p2v (_RSRR)))
#define RCSR    	        	/* RC Status Reg.                  */ \
                	(*((volatile Word *) io_p2v (_RCSR)))

#define RSRR_SWR	0x00000001	/* SoftWare Reset (set only)       */

#define RCSR_HWR	0x00000001	/* HardWare Reset                  */
#define RCSR_SWR	0x00000002	/* SoftWare Reset                  */
#define RCSR_WDR	0x00000004	/* Watch-Dog Reset                 */
#define RCSR_SMR	0x00000008	/* Sleep-Mode Reset                */

#endif //_SA1110_HEADER_