stm32f10x_svpwm_1shunt.c

ARM_CORTEX-M3应用实例开发详解光盘

      
	    if (bStatorFluxPos == BOUNDARY_2)
	    {
	      hCurrA += hDeltaA;
	      hCurrB += hDeltaB;
	      hCurrC += hDeltaC;
	    }
	#endif
    
    hCurrAOld = hCurrA;
    hCurrBOld = hCurrB;
    hCurrCOld = hCurrC;

    Local_Stator_Currents.qI_Component1 = hCurrA;
    Local_Stator_Currents.qI_Component2 = hCurrB;
    
    return(Local_Stator_Currents); 
}

/*******************************************************************************
* Function Name  : SVPWM_1ShuntAdvCurrentReading
* Description    :  It is used to enable or disable the current reading.
* Input          : cmd (ENABLE or DISABLE)
* Output         : None
* Return         : None
*******************************************************************************/
void SVPWM_1ShuntAdvCurrentReading(FunctionalState cmd)
{
  if (cmd == ENABLE)
  {
    // Enable UPDATE ISR
    // Clear Update Flag
    TIM_ClearFlag(TIM1, TIM_FLAG_Update);
    TIM_ITConfig(TIM1, TIM_IT_Update, ENABLE);
    
    // Distortion for single shunt enabling
    bDistEnab = 1;
  }
  else
  {
    // Disable UPDATE ISR
    TIM_ITConfig(TIM1, TIM_IT_Update, DISABLE);

    // Sync ADC trigger with Update
    ADC_ExternalTrigInjectedConvConfig(ADC1, ADC_ExternalTrigInjecConv_T1_TRGO);

	// Enabling the Injectec conversion for ADC1
  	ADC_ExternalTrigInjectedConvCmd(ADC1,ENABLE);
    
    // Clear pending bit and Enable the EOC ISR
    ADC_ClearFlag(ADC1, ADC_FLAG_JEOC);
    ADC_ITConfig(ADC1, ADC_IT_JEOC, ENABLE);
    
    // Distortion for single shunt disabling
    bDistEnab = 0;
    
    // Disabling the last setting of PWM Mode and Duty Register
    hPreloadCCMR1Set = hPreloadCCMR1Disable | CH1NORMAL | CH2NORMAL;
    hPreloadCCMR2Set = hPreloadCCMR2Disable | CH3NORMAL | CH4NORMAL;
    TIM1->CCMR1 = hPreloadCCMR1Set; // Switch to Normal 
    TIM1->CCMR2 = hPreloadCCMR2Set; // Switch to Normal
    
    // Disabling all DMA previous setting
    TIM_DMACmd(TIM1, TIM_DMA_CC1, DISABLE);
    TIM_DMACmd(TIM1, TIM_DMA_CC2, DISABLE);
    TIM_DMACmd(TIM1, TIM_DMA_CC3, DISABLE);
    
    // Set all duty to 50%
    TIM1->CCR1 = PWM_PERIOD >> 1;
    TIM1->CCR2 = PWM_PERIOD >> 1;
    TIM1->CCR3 = PWM_PERIOD >> 1;    
  }
}

/*******************************************************************************
* Function Name  : SVPWMEOCEvent
* Description    :  Routine to be performed inside the end of conversion ISR
			store the first sampled value and compute the bus voltage and temperature
			sensor sampling  and disable the ext. adc triggering.
* Input           : None
* Output         : Return false after first EOC, return true after second EOC
* Return         : None
*******************************************************************************/
u8 SVPWMEOCEvent(void)
{
  if (bDistEnab == 1)
  {
    // Diabling the Injectec conversion for ADC1
    ADC_ExternalTrigInjectedConvCmd(ADC1,DISABLE);
  }
  
  // Store the Bus Voltage and temperature sampled values
  h_ADCTemp = ADC_GetInjectedConversionValue(ADC2,ADC_InjectedChannel_1);
  h_ADCBusvolt = ADC_GetInjectedConversionValue(ADC2,ADC_InjectedChannel_2);
  
  return ((u8)(1));
}

/*******************************************************************************
* Function Name  : SVPWMUpdateEvent
* Description    :  Routine to be performed inside the update event ISR. 
                    It is used to set the PWM output mode of the four channels 
                    (Toggle or PWM), enable or disable the DMA event for each 
                    channel, update the DMA buffers, update the DMA lenght and 
                    finally it re-enables the external ADC triggering.	
* Input           : None
* Output         : None
* Return         : None
*******************************************************************************/
void SVPWMUpdateEvent(void)
{
  if (bInverted_pwm_new != bInverted_pwm)  
  {
    // Critical point start
    
    // Update CCMR (OC Mode)
    TIM1->CCMR1 = hPreloadCCMR1Disable; // Switch to Frozen
    TIM1->CCMR1 = hPreloadCCMR1Set; // Switch to Normal or Toggle
    
    TIM1->CCMR2 = hPreloadCCMR2Disable; // Switch to Frozen
    TIM1->CCMR2 = hPreloadCCMR2Set; // Switch to Normal or Toggle
    
    // Disable DMA (in this period is not inverted)
    switch (bInverted_pwm)
    {
    case INVERT_A:
      //TIM1_DMACmd(TIM1_DMA_CC1, DISABLE);
      TIM1->DIER &= ~TIM_DMA_CC1;
      DMA1_Channel2->CCR &= CCR_ENABLE_Reset;
      TIM1->CCR1 = hCCRBuff[0];
      break;
    case INVERT_B:
      //TIM1_DMACmd(TIM1_DMA_CC2, DISABLE);
      TIM1->DIER &= ~TIM_DMA_CC2;
      DMA1_Channel3->CCR &= CCR_ENABLE_Reset;
      TIM1->CCR2 = hCCRBuff[1];
      break;
    case INVERT_C:
      //TIM1_DMACmd(TIM1_DMA_CC3, DISABLE);
      TIM1->DIER &= ~TIM_DMA_CC3;
      DMA1_Channel6->CCR &= CCR_ENABLE_Reset;
      TIM1->CCR3 = hCCRBuff[2];
      break;
    default:
      break;
    }
    
    // Enable DMA (in this period channel is toggled)
    switch (bInverted_pwm_new)
    {
    case INVERT_A:
      DMA1_Channel2->CCR &= CCR_ENABLE_Reset;
      DMA1_Channel2->CNDTR = 4;
      DMA1_Channel2->CCR |= CCR_ENABLE_Set;
      
      //TIM1_DMACmd(TIM1_DMA_CC1, ENABLE); 
      TIM1->DIER |= TIM_DMA_CC1;  
      
      if (bInverted_pwm_new == INVERT_A)
      {
        if (hCCRBuff[0] <= MINTIMCNTUPHAND)
        {
          TIM1->CCMR1 = TIM1->CCMR1 & 0xFF8F; // Switch to Frozen Ch1
          TIM1->CCMR1 = TIM1->CCMR1 | 0x0040; // Force Low Ch1
          TIM1->CCMR1 = TIM1->CCMR1 & 0xFF8F; // Switch to Frozen Ch1
          TIM1->CCMR1 = TIM1->CCMR1 | 0x0030; // Switch to Toggle Ch1
          
          //TIM1_GenerateEvent(TIM1_EventSource_CC1);
          TIM1->EGR |= TIM_EventSource_CC1;
        }
      }
      break;
      
    case INVERT_B:
      DMA1_Channel3->CCR &= CCR_ENABLE_Reset;
      DMA1_Channel3->CNDTR = 4;
      DMA1_Channel3->CCR |= CCR_ENABLE_Set;
      
      //TIM1_DMACmd(TIM1_DMA_CC2, ENABLE); 
      TIM1->DIER |= TIM_DMA_CC2;
      
      if (bInverted_pwm_new == INVERT_B)
      {
        if (hCCRBuff[1] <= MINTIMCNTUPHAND)
        {
          TIM1->CCMR1 = TIM1->CCMR1 & 0x8FFF; // Switch to Frozen Ch2
          TIM1->CCMR1 = TIM1->CCMR1 | 0x4000; // Force Low Ch2
          TIM1->CCMR1 = TIM1->CCMR1 & 0x8FFF; // Switch to Frozen Ch2
          TIM1->CCMR1 = TIM1->CCMR1 | 0x3000; // Switch to Toggle Ch2
          
          //TIM1_GenerateEvent(TIM1_EventSource_CC2);
          TIM1->EGR |= TIM_EventSource_CC2;
        }
      }
      break;
      
    case INVERT_C:
      DMA1_Channel6->CCR &= CCR_ENABLE_Reset;
      DMA1_Channel6->CNDTR = 4;
      DMA1_Channel6->CCR |= CCR_ENABLE_Set;
      
      //TIM1_DMACmd(TIM1_DMA_CC3, ENABLE);
      TIM1->DIER |= TIM_DMA_CC3;
      
      if (bInverted_pwm_new == INVERT_C)
      {
        if (hCCRBuff[2] <= MINTIMCNTUPHAND)
        {
          TIM1->CCMR2 = TIM1->CCMR2 & 0xFF8F; // Switch to Frozen Ch3
          TIM1->CCMR2 = TIM1->CCMR2 | 0x0040; // Force Low Ch3
          TIM1->CCMR2 = TIM1->CCMR2 & 0xFF8F; // Switch to Frozen Ch3
          TIM1->CCMR2 = TIM1->CCMR2 | 0x0030; // Switch to Toggle Ch3
          
          //TIM1_GenerateEvent(TIM1_EventSource_CC3);
          TIM1->EGR |= TIM_EventSource_CC3;
        }
      }
      break;
      
    default:
      break;
    }
    
    // Critical point stop
    
    // Adjust the DMA lenght for Ch4
    //DMA_Cmd(DMA_Channel4, DISABLE);
    DMA1_Channel4->CCR &= CCR_ENABLE_Reset;
    if (bInverted_pwm_new == INVERT_NONE)
    { 
      // Length 2
      DMA1_Channel4->CNDTR = 2;
    }
    else
    {
      // Length 4
      DMA1_Channel4->CNDTR = 4;
    }
    //DMA_Cmd(DMA_Channel4, ENABLE);
    DMA1_Channel4->CCR |= CCR_ENABLE_Set;
  }
  
  switch (bInverted_pwm_new)
  {
  case INVERT_A: 
    if (hCCRBuff[0] <= DMABURSTMIN_A)
    {
      // Reset the status
      TIM1->CCMR1 = TIM1->CCMR1 & 0xFF8F; // Switch to Frozen Ch1
      TIM1->CCMR1 = TIM1->CCMR1 | 0x0040; // Force Low Ch1
      TIM1->CCMR1 = TIM1->CCMR1 & 0xFF8F; // Switch to Frozen Ch1
      TIM1->CCMR1 = TIM1->CCMR1 | 0x0030; // Switch to Toggle Ch1
      
      //TIM1_DMACmd(TIM1_DMA_CC1, ENABLE); 
      TIM1->DIER |= TIM_DMA_CC1;
      DMA1_Channel2->CCR &= CCR_ENABLE_Reset;
      DMA1_Channel2->CNDTR = 4;
      DMA1_Channel2->CCR |= CCR_ENABLE_Set;

      TIM_GenerateEvent(TIM1, TIM_EventSource_CC1);
      
      if (dvDutyValues.hTimePhA < DMABURSTMIN_A)
        dvDutyValues.hTimePhA = DMABURSTMIN_A;
    }
    break;  
      
  case INVERT_B:
    if (hCCRBuff[1] <= DMABURSTMIN_B)
    {
      // Reset the status
      TIM1->CCMR1 = TIM1->CCMR1 & 0x8FFF; // Switch to Frozen Ch2
      TIM1->CCMR1 = TIM1->CCMR1 | 0x4000; // Force Low Ch2
      TIM1->CCMR1 = TIM1->CCMR1 & 0x8FFF; // Switch to Frozen Ch2
      TIM1->CCMR1 = TIM1->CCMR1 | 0x3000; // Switch to Toggle Ch2
      
      //TIM1_DMACmd(TIM1_DMA_CC2, ENABLE); 
      TIM1->DIER |= TIM_DMA_CC2;
      DMA1_Channel3->CCR &= CCR_ENABLE_Reset;
      DMA1_Channel3->CNDTR = 4;
      DMA1_Channel3->CCR |= CCR_ENABLE_Set;

      TIM_GenerateEvent(TIM1, TIM_EventSource_CC2);
      
      if (dvDutyValues.hTimePhB < DMABURSTMIN_B)
        dvDutyValues.hTimePhB = DMABURSTMIN_B;
    }
    break;
  case INVERT_C: 
    if (hCCRBuff[2] <= DMABURSTMIN_C)
    {
      // Reset the status
      TIM1->CCMR2 = TIM1->CCMR2 & 0xFF8F; // Switch to Frozen Ch3
      TIM1->CCMR2 = TIM1->CCMR2 | 0x0040; // Force Low Ch3
      TIM1->CCMR2 = TIM1->CCMR2 & 0xFF8F; // Switch to Frozen Ch3
      TIM1->CCMR2 = TIM1->CCMR2 | 0x0030; // Switch to Toggle Ch3
      
      //TIM1_DMACmd(TIM1_DMA_CC3, ENABLE); 
      TIM1->DIER |= TIM_DMA_CC3;
      DMA1_Channel6->CCR &= CCR_ENABLE_Reset;
      DMA1_Channel6->CNDTR = 4;
      DMA1_Channel6->CCR |= CCR_ENABLE_Set;

      TIM_GenerateEvent(TIM1, TIM_EventSource_CC3);
      
      if (dvDutyValues.hTimePhC < DMABURSTMIN_C)
        dvDutyValues.hTimePhC = DMABURSTMIN_C;
    }
    break;
  }

  // Update remaining DMA buffer
  hCCDmaBuffCh4[0] = dvDutyValues.hTimeSmp2; // Second point 
  hCCDmaBuffCh4[1] = dvDutyValues.hTimeSmp2;
  hCCDmaBuffCh4[2] = dvDutyValues.hTimeSmp1; // First point
  hCCDmaBuffCh4[3] = dvDutyValues.hTimeSmp1;
  
  hCCDmaBuffCh1[2] = dvDutyValues.hTimePhA;
  hCCDmaBuffCh1[3] = dvDutyValues.hTimePhA;
  
  hCCDmaBuffCh2[2] = dvDutyValues.hTimePhB;
  hCCDmaBuffCh2[3] = dvDutyValues.hTimePhB;
  
  hCCDmaBuffCh3[2] = dvDutyValues.hTimePhC;
  hCCDmaBuffCh3[3] = dvDutyValues.hTimePhC;
  
  bInverted_pwm = bInverted_pwm_new;
  
  /* ADC1 Injected conversions trigger is TIM1 TRGO */ 
  ADC_ExternalTrigInjectedConvConfig(ADC1, ADC_ExternalTrigInjecConv_T1_CC4); 
  
  // Enabling the Injectec conversion for ADC1
  ADC_ExternalTrigInjectedConvCmd(ADC1,ENABLE);
}


#endif

/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/