dsp32.h

speech signal process tools

struct	{
	char name[12];
	int  value;
} typedef SYMBOL;

#define	NDATA	12

struct	d_cmd {
	short	status;
	short	c_cnt;
	short	o_cnt;
	short	cmd;
	short	data[NDATA];
};

#define	b_cnt	data[0]
#define	b_addrs	data[1]
#define	b_high	data[2]
#define	b_low	data[3]
#define	d_data	data[0]
#define	d_emr	data[1]

#define	t_cntr	data[4]
#define	t_mode	data[5]
#define	t_low	data[6]
#define	t_high	data[7]
#define	t_run	data[8]
#define	t_stop	data[9]

#define	DSPGT(x)	(((x)>>10)&0x3)
#define	DSPST(x)	(((x)&0x3f)<<10)
#define	BOARDGT(x)	(((x)>>12)&0xf)
#define	BOARDST(x)	(((x)&0xf)<<12)
#define	DSP_DPR		128
#define	DSP_SLV		64

#define	SIGDSP		31

#ifdef	_IOWR		/* SUN3 */

#define	DIOCTL		_IOWR(d, 1, struct d_cmd)
#define	DIOSCTL		_IOWR(d, 2, struct ds_priv)

#else			/* 3b2 */

#define	DSPIOC		('D'<<8)
#define	DIOCTL		(DSPIOC|0)
#define	DIOSCTL		(DSPIOC|1)
#endif

#ifdef HP300
#define	DSPIOC		('D'<<8)
#define	DIOCTL		(DSPIOC|0)
#define	DIOSCTL		(DSPIOC|1)
#endif

#define	C_WRITE		0x0200
#define	C_IRQ		0x0100
#define	C_BLOCK		0x0080
#define	C_VME_ADDRS	0x0040
#define	C_SLAVE_SRAM	0x0020
#define	C_SLAVE_DPR	0x0010
#define	C_SLAVE_RW	0x0008

#define	C_REGISTER	0x0040
#define	C_PDR_CASH	0x0072
#define	C_SHORT		0x0010

#define	C_PAR		0x50
#define	C_PDR		0x52
#define	C_EMR		0x54
#define	C_ESR		0x46
#define	C_PCR		0x47
#define	C_PIR		0x58

#define	C_RDV		0x10
#define	C_RUN		0x11
#define	C_STOP		0x12
#define	C_INT		0x13
#define	C_CSR		0x14
#define	C_NEWCNT	0x15
#define	C_SIG		0x16
#define	C_CLRSIG	0x17
#define	C_TIMER		0x18
#define	C_SYSID		0x19
#define	C_68k		0x1a
#define	C_KILL		0x1f

#define	S_BUSY		0x01
#define	S_LOCKED	0x02
#define	S_READY		0x04		/* fake used buy driver */
#define	S_PDR_CASH	0x10
#define	S_BLOCK		0x20
#define	S_UDPERR	0x0100
#define	S_TIMEOUT	0x0200
#define	S_NOCMD		0x1000
#define	S_BUSERR 	0x2000
#define	S_ERROR		0x8000

/*	9513 timer modes			*/

#define	TMR_MODE	0x0b62		/* free running, F1 clock */
#define	TMR_GATE	0xe000		/* gate N */

/*	DSP32 VMEbus board control register	*/

#define	CSR_PGA_MM0	0x01		/* PGA memory mode bits */
#define	CSR_PGA_MM1	0x02
					/* old board */
#define	CSR_TAB		0x04		/* PGA TAB (test pin, set to 0) */
					/* NC in final spec	*/
#define	CSR_ZN		0x08		/* PGA ZN (common enable, set to 1) */
					/* new board */
#define	CSR_ENI_DPI0	0x04		/* DIP0 interrupt enable */
#define	CSR_ENI_DPI1	0x08		/* DIP1 interrupt enable */
#define	CSR_ENI		0x10		/* DSP interrupt enable */
#define	CSR_DIP0_MM	0x20		/* DIP memory mode bits (mode 0/3) */
#define	CSR_DIP1_MM	0x40
#define	CSR_ENABLE	0x80		/* DSP hardware reset */

#define	CSR_DEFAULT	0xea		/* memory mode 2/3/3, no interupt, enabled */
#define	CSR_RESET	0x6a		/* reset all DSP32's */

/*	DSP32 parallel control register bits	*/

#define	PCR_RUN		0x01
#define	PCR_I16		0x02
#define	PCR_ENI		0x04
#define	PCR_DMA		0x08
#define	PCR_AUTO	0x10
#define	PCR_PDF		0x20
#define	PCR_PIF		0x40
#define	PCR_NORFRS	0x80

#define	DMA_MODE	(PCR_DMA|PCR_AUTO|PCR_I16)

/*	DSP32 error source register bits		*/

#define	ESR_PIF		0x04
#define	ESR_IPrty	0x08
#define	ESR_DAU		0x10
#define	ESR_ADR		0x20
#define	ESR_SAN		0x40
#define	ESR_SYNC	0x80

/*	DSP32 error mask register parts		*/

#define	EMR_DEF		0xffff
#define	EMR_PINT(x)	(x)
#define	EMR_ABORT(x)	( (x<<8)|x )