jit-sparc.def

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/* jit-sparc.def
 * SPARC instruction definition.
 *
 * Copyright (c) 1996, 1997
 *	Transvirtual Technologies, Inc.  All rights reserved.
 *
 * See the file "license.terms" for information on usage and redistribution 
 * of this file. 
 */

#ifdef KAFFE_VMDEBUG
int jit_debug;
#define debug(x)        (jit_debug ? dprintf("%x:\t", CODEPC), dprintf x : 0)
#else
#define debug(x)
#endif

#include "classMethod.h"
#include "access.h"
#include "gtypes.h"

#define	REG_g0			0
#define	REG_o0			8
#define	REG_o1			9
#define	REG_sp			14
#define	REG_o7			15
#define	REG_i0			24
#define	REG_i1			25
#define	REG_fp			30
#define	REG_i7			31
#define	REG_f0			32
#define	REG_f1			33

#ifdef KAFFE_VMDEBUG
static char* rnames[] = {
	"g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
	"o0", "o1", "o2", "o3", "o4", "o5", "o6", "o7",
	"l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
	"i0", "i1", "i2", "i3", "i4", "i5", "i6", "i7",
	"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
	"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
	"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", "f24",
	"f25", "f26", "f27", "f28", "f29", "f30", "f31"			};
#define	regname(n)	rnames[n]
#define	fregname(n)	rnames[(n)+32]
#endif

static int argcount = 0;

/* --------------------------------------------------------------------- */
/* Instruction formats							 */

#define	insn_call(disp)					\
	LOUT = 0x40000000 | ((disp) & 0x3FFFFFFF)

#define	insn_offset(op, dst, imm)			\
	LOUT = 0x01000000 | ((dst) << 25) | 		\
		((op) << 22) | ((imm) & 0x3FFFFF)

#define	insn_branch(cond, anull, dest)			\
	LOUT = 0x00800000 | ((anull) << 29) |		\
		((cond) << 25) | ((dest) & 0x3FFFFF)

#define	insn_RRR(op, dst, rs1, rs2)			\
	LOUT = 0x80000000 | ((dst) << 25) |		\
		((op) << 19) | ((rs1) << 14) | (rs2)

#define	ldst_RRR(op, dst, rs1, rs2)			\
	LOUT = 0xC0000000 | ((dst) << 25) |		\
		((op) << 19) | ((rs1) << 14) | (rs2)

#define	ldst_RRC(op, dst, rs1, cnst)			\
	LOUT = 0xC0002000 | ((dst) << 25) |		\
		((op) << 19) | ((rs1) << 14) |		\
		((cnst) & MASKL13BITS)

#define	insn_RRC(op, op2, dst, rs1, cnst)		\
	LOUT = 0x00002000 | ((op) << 30) |		\
		((dst) << 25) | ((op2) << 19) |		\
		((rs1) << 14) | ((cnst) & MASKL13BITS)

#define	finsn_RRR(op, dst, rs1, rs2)			\
	LOUT = 0x81A00000 | ((dst) << 25) |	\
		((rs1) << 14) | ((op) << 5) |	\
		(rs2)

/* --------------------------------------------------------------------- */
/* Various masks							 */

#define	MASKL12BITS	0x00000FFF
#define	MASKL13BITS	0x00001FFF
#define	MASKU20BITS	0xFFFFFC00

#define	NMASKL12BITS	(~MASKL12BITS)
#define	NMASKL13BITS	(~MASKL13BITS)
#define	NMASKU20BITS	(~MASKU20BITS)

/* --------------------------------------------------------------------- */

#define	NOP()	insn_offset(4, REG_g0, 0);		\
		debug(("nop\n"));

define_insn(unimplemented, unimplemented)
{
	ABORT();
}

define_insn(nop, nop)
{
	NOP();
}

/* --------------------------------------------------------------------- */

define_insn(prologue, prologue_xLC)
{
	int i;
	int limit;
	label* l;

	/* Remember where the framesize should go */
	l = (label*)const_int(1);
	l->type = Lframe|Labsolute|Lgeneral;
	l->at = (uintp)CODEPC;

	insn_RRC(2, 0x3c, REG_sp, REG_sp, 0);

	debug(("save sp,?,sp\n"));

	limit = 6;
	if (maxArgs < limit) {
		limit = maxArgs;
	}

	/* Force the first 6 arguments to the corresponding registers */
	for (i = 0; i < limit; i++) {
		forceRegister(&localinfo[i], REG_i0 + i, Rint /* ? */);
	}
}

define_insn(epilogue, epilogue_xxx)
{
	setEpilogueLabel ((uintp)CODEPC);

	insn_RRC(2, 0x38, REG_g0, REG_i7, 8);
	insn_RRR(0x3D, REG_g0, REG_g0, REG_g0);

	debug(("ret\n"));
	debug(("restore\n"));
}

define_insn(eprologue, eprologue_xxx)
{
}

/* --------------------------------------------------------------------- */

define_insn(spill_int, spill_Rxx)
{
	int r = sreg_int(0);
	int o = const_int(1);

	ldst_RRC(0x04, r, REG_fp, o);

	debug(("st %s,[fp+%d]\n", regname(r), o));
}

define_insn(spill_float, fspill_Rxx)
{
	int r = sreg_float(0);
	int o = const_int(1);

	ldst_RRC(0x24, r, REG_fp, o);

	debug(("stf %s,[fp+%d]\n", fregname(r), o));
}

define_insn(spill_double, fspilll_Rxx)
{
	int r = sreg_double(0);
	int o = const_int(1);

	ldst_RRC(0x24, r, REG_fp, o);
	debug(("stf %s,[fp+%d]\n", fregname(r), o));

	ldst_RRC(0x24, r+1, REG_fp, o+4);
	debug(("stf %s,[fp+%d]\n", fregname(r+1), o+4));
}

define_insn(reload_int, reload_Rxx)
{
	int r = lreg_int(0);
	int o = const_int(1);

	ldst_RRC(0, r, REG_fp, o);

	debug(("ld %s,[fp+%d]\n", regname(r), o));
}

define_insn(reload_float, freload_Rxx)
{
	int r = lreg_float(0);
	int o = const_int(1);

	ldst_RRC(0x20, r, REG_fp, o);

	debug(("ldf %s,[fp+%d]\n", fregname(r), o));
}

define_insn(reload_double, freloadl_Rxx)
{
	int r = lreg_double(0);
	int o = const_int(1);

	ldst_RRC(0x20, r, REG_fp, o);
	debug(("ldf %s,[fp+%d]\n", fregname(r), o));

	ldst_RRC(0x20, r+1, REG_fp, o+4);
	debug(("ldf %s,%d[fp]\n", fregname(r+1), o+4));
}

/* --------------------------------------------------------------------- */

define_insn(move_int_const, move_RxC)
{
	int val = const_int(2);
	int w = wreg_int(0);

	if ((val & NMASKL12BITS) == 0 || (val & NMASKL12BITS) == NMASKL12BITS) {
		insn_RRC(2, 2, w, REG_g0, val & MASKL13BITS);
		debug(("mov %d,%s\n", val & MASKL13BITS, regname(w)));
	}
	else {
		insn_offset(4, w, val >> 10);
		debug(("sethi 0x%x,%s ; 0x%x\n", val & MASKU20BITS, regname(w), val));
		if ((val & NMASKU20BITS) != 0) {
			insn_RRC(2, 2, w, w, val & NMASKU20BITS);
			debug(("or 0x%x,%s,%s\n", val & NMASKU20BITS, regname(w), regname(w)));
		}
	}
}

define_insn(move_label_const, move_RxL)
{
	label* l = (label*)const_int(2);
	int w = wreg_int(0);

	l->type |= Llong22x10|Labsolute;
	l->at = (uintp)CODEPC;

	insn_offset(4, w, 0);		/* upper 22 bits */
	insn_RRC(2, 2, w, w, 0);	/* lower 10 bits */
	debug(("sethi ?,%s\n", regname(w)));
	debug(("or ?,%s,%s\n", regname(w), regname(w)));
}

define_insn(move_int, move_RxR)
{
	int r = rreg_int(2);
	int w = wreg_int(0);

	if (r != w) {
		insn_RRR(2, w, r, REG_g0);
		debug(("mov %s,%s\n", regname(r), regname(w)));
	}
}

define_insn(move_float, fmove_RxR)
{
	int r = rreg_float(2);
	int w = wreg_float(0);

	if (r != w) {
		finsn_RRR(1, w, 0, r);
		debug(("fmovs %s,%s\n", fregname(r), fregname(w)));
	}
}

define_insn(move_double, fmovel_RxR)
{
	int r = rreg_double(2);
	int w = wreg_double(0);

	if (r != w) {
		finsn_RRR(1, w, 0, r);
		finsn_RRR(1, w+1, 0, r+1);
		debug(("fmovs %s,%s\n", fregname(r), fregname(w)));
		debug(("fmovs %s,%s\n", fregname(r+1), fregname(w+1)));
	}
}

/* --------------------------------------------------------------------- */

define_insn(add_int, add_RRR)
{
	int r1;
	int r2;
	int w;

	r2 = rreg_int(2);
	r1 = rreg_int(1);
	w = wreg_int(0);

	insn_RRR(0x10, w, r1, r2);

	debug(("addcc %s,%s,%s\n", regname(r1), regname(r2), regname(w)));
}

define_insn(add_int_const, add_RRC)
{
	int o;
	int r;
	int w;

	o = const_int(2);
	r = rreg_int(1);
	w = wreg_int(0);

	insn_RRC(2, 0x10, w, r, o);

	debug(("addcc %s,%d,%s\n", regname(r), o, regname(w)));
}

define_insn(adc_int, adc_RRR)
{
	int r1;
	int r2;
	int w;

	r2 = rreg_int(2);
	r1 = rreg_int(1);
	w = wreg_int(0);

	insn_RRR(0x08, w, r1, r2);

	debug(("addx %s,%s,%s\n", regname(r1), regname(r2), regname(w)));
}

define_insn(add_float, fadd_RRR)
{
	int r1;
	int r2;
	int w;

	r2 = rreg_float(2);
	r1 = rreg_float(1);
	w = wreg_float(0);

	finsn_RRR(0x41, w, r1, r2);

	debug(("fadds %s,%s,%s\n", fregname(r1), fregname(r2), fregname(w)));
}

define_insn(add_double, faddl_RRR)
{
	int r1;
	int r2;
	int w;

	r2 = rreg_double(2);
	r1 = rreg_double(1);
	w = wreg_double(0);

	finsn_RRR(0x42, w, r1, r2);

	debug(("faddd %s,%s,%s\n", fregname(r1), fregname(r2), fregname(w)));
}

define_insn(sub_int, sub_RRR)
{
	int r1;
	int r2;
	int w;

	r2 = rreg_int(2);
	r1 = rreg_int(1);
	w = wreg_int(0);

	insn_RRR(0x14, w, r1, r2);

	debug(("subcc %s,%s,%s\n", regname(r1), regname(r2), regname(w)));
}

define_insn(sub_int_const, sub_RRC)
{
	int o;
	int r;
	int w;

	o = const_int(2);
	r = rreg_int(1);
	w = wreg_int(0);

	insn_RRC(2, 0x14, w, r, o);

	debug(("subcc %s,%d,%s\n", regname(r), o, regname(w)));
}

define_insn(sbc_int, sbc_RRR)
{
	int r1;
	int r2;
	int w;

	r2 = rreg_int(2);
	r1 = rreg_int(1);
	w = wreg_int(0);

	insn_RRR(0xC, w, r1, r2);

	debug(("subx %s,%s,%s\n", regname(r1), regname(r2), regname(w)));
}

define_insn(sub_float, fsub_RRR)
{
	int r1;
	int r2;
	int w;

	r2 = rreg_float(2);
	r1 = rreg_float(1);
	w = wreg_float(0);

	finsn_RRR(0x45, w, r1, r2);

	debug(("fsubs %s,%s,%s\n", fregname(r1), fregname(r2), fregname(w)));
}

define_insn(sub_double, fsubl_RRR)
{
	int r1;
	int r2;
	int w;

	r2 = rreg_double(2);
	r1 = rreg_double(1);
	w = wreg_double(0);

	finsn_RRR(0x46, w, r1, r2);

	debug(("fsubd %s,%s,%s\n", fregname(r1), fregname(r2), fregname(w)));
}

define_insn(mul_float, fmul_RRR)
{
	int r1;
	int r2;
	int w;

	r2 = rreg_float(2);
	r1 = rreg_float(1);
	w = wreg_float(0);

	finsn_RRR(0x49, w, r1, r2);

	debug(("fmuls %s,%s,%s\n", fregname(r1), fregname(r2), fregname(w)));
}

define_insn(mul_double, fmull_RRR)
{
	int r1;
	int r2;
	int w;

	r2 = rreg_double(2);
	r1 = rreg_double(1);
	w = wreg_double(0);

	finsn_RRR(0x4A, w, r1, r2);

	debug(("fmuld %s,%s,%s\n", fregname(r1), fregname(r2), fregname(w)));
}

define_insn(div_float, fdiv_RRR)
{
	int r1;
	int r2;
	int w;

	r2 = rreg_float(2);
	r1 = rreg_float(1);
	w = wreg_float(0);

	finsn_RRR(0x4D, w, r1, r2);

	debug(("fdivs %s,%s,%s\n", fregname(r1), fregname(r2), fregname(w)));
}

define_insn(div_double, fdivl_RRR)
{
	int r1;
	int r2;
	int w;

	r2 = rreg_double(2);
	r1 = rreg_double(1);
	w = wreg_double(0);

	finsn_RRR(0x4E, w, r1, r2);

	debug(("fdivd %s,%s,%s\n", fregname(r1), fregname(r2), fregname(w)));
}

define_insn(neg_float, fneg_RxR)
{
	int r = rreg_float(2);
	int w = wreg_float(0);

	finsn_RRR(5, w, 0, r);
	debug(("fnegs %s,%s\n", fregname(r), fregname(w)));
}

define_insn(neg_double, fnegl_RxR)
{
	int r = rreg_double(2);
	int w = wreg_double(0);

	finsn_RRR(5, w, 0, r);
	debug(("fnegs %s,%s\n", fregname(r), fregname(w)));
	if (r != w) {
		finsn_RRR(1, w+1, 0, r+1);
		debug(("fmovs %s,%s\n", fregname(r+1), fregname(w+1)));
	}
}

/* --------------------------------------------------------------------- */

define_insn(and_int, and_RRR)
{
	int r1;
	int r2;
	int w;

	r2 = rreg_int(2);
	r1 = rreg_int(1);
	w = wreg_int(0);

	insn_RRR(1, w, r1, r2);

	debug(("and %s,%s,%s\n", regname(r1), regname(r2), regname(w)));
}

define_insn(or_int, or_RRR)
{
	int r1;
	int r2;
	int w;

	r2 = rreg_int(2);
	r1 = rreg_int(1);
	w = wreg_int(0);

	insn_RRR(2, w, r1, r2);

	debug(("or %s,%s,%s\n", regname(r1), regname(r2), regname(w)));
}

define_insn(xor_int, xor_RRR)
{
	int r1;
	int r2;
	int w;

	r2 = rreg_int(2);
	r1 = rreg_int(1);
	w = wreg_int(0);

	insn_RRR(3, w, r1, r2);

	debug(("xor %s,%s,%s\n", regname(r1), regname(r2), regname(w)));
}

define_insn(ashr_int, ashr_RRR)
{
	int r1;
	int r2;
	int w;

	r2 = rreg_int(2);
	r1 = rreg_int(1);
	w = wreg_int(0);

	insn_RRR(0x27, w, r1, r2);

	debug(("sra %s,%s,%s\n", regname(r1), regname(r2), regname(w)));
}

define_insn(lshr_int, lshr_RRR)
{
	int r1;
	int r2;
	int w;

	r2 = rreg_int(2);
	r1 = rreg_int(1);
	w = wreg_int(0);

	insn_RRR(0x26, w, r1, r2);