jit-i386.def

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	assert(r != REG_eax);
	assert(r != REG_edx);

	/* special case for LONG_MIN % -1l: r == -1 ? 0 : eax / r  */
	OUT = 0x83;
	OUT = 0xF8|r;
	OUT = 0xFF;
	debug(("cmp #0xFF,%s\n", regname(r)));

	l1 = newLabel();
	l1->type = Linternal| Llong8|Lrelative;
	OUT = 0x74;
	l1->at = CODEPC;
	OUT = 0;
	l1->from = CODEPC;
	debug(("je const0\n"));

	/* Setup EDX - should contains the sign of EAX */
	do_move_int(REG_edx, REG_eax);
#if 0
	OUT = 0xC1;
	OUT = 0xF8|REG_edx;
	OUT = 31;
	debug(("sarl #31,edx\n"));
#else
	OUT = 0x99;
	debug(("cltd\n"));
#endif

	OUT = 0xF7;
        OUT = 0xF8|r;
	debug(("idivl %s,%s\n", regname(r), regname(w)));

	OUT = 0xEB;
	OUT = 2;
	debug(("jmp +2\n"));

	debug(("const0:\n"));
	l1->to = CODEPC;
	OUT = 0x31;
        OUT = 0xC0|(REG_edx<<3)|REG_edx;
	debug(("xorl edx,edx\n"));

	/* Result is in EDX not EAX - we must force the slot register */
	forceRegister(seq_dst(s), REG_edx, Rint);
}

/* --------------------------------------------------------------------- */

define_insn(and_int, and_RRR)
{
	int r;
	int w;

	check_reg_01();

	r = rreg_int(2);
	w = rwreg_int(0);

	OUT = 0x21;
        OUT = 0xC0|(r<<3)|w;

	debug(("andl %s,%s\n", regname(r), regname(w)));
}

define_insn(or_int, or_RRR)
{
	int r;
	int w;

	check_reg_01();

	r = rreg_int(2);
	w = rwreg_int(0);

	OUT = 0x09;
        OUT = 0xC0|(r<<3)|w;

	debug(("orl %s,%s\n", regname(r), regname(w)));
}

define_insn(xor_int, xor_RRR)
{
	int r;
	int w;

	check_reg_01();

	r = rreg_int(2);
	w = rwreg_int(0);

	OUT = 0x31;
        OUT = 0xC0|(r<<3)|w;

	debug(("xorl %s,%s\n", regname(r), regname(w)));
}

define_insn(ashr_int, ashr_RRR)
{
	int r;
	int w;

	check_reg_01();

	r = rreg_int(2);

	/* Can only shift by ECX. */
	do_force_move_int(REG_ecx, r, 2);

	w = rwreg_int(0);

	OUT = 0xD3;
        OUT = 0xF8|w;

	debug(("sarl %s,%s\n", regname(r), regname(w)));
}

define_insn(lshr_int, lshr_RRR)
{
	int r;
	int w;

	check_reg_01();

	r = rreg_int(2);

	/* Can only shift by ECX. */
	do_force_move_int(REG_ecx, r, 2);

	w = rwreg_int(0);

	OUT = 0xD3;
        OUT = 0xE8|w;

	debug(("shrl %s,%s\n", regname(r), regname(w)));
}

define_insn(lshl_int, lshl_RRR)
{
	int r;
	int w;

	check_reg_01();

	r = rreg_int(2);

	/* Can only shift by ECX. */
	do_force_move_int(REG_ecx, r, 2);

	w = rwreg_int(0);

	OUT = 0xD3;
        OUT = 0xE0|w;

	debug(("shll %s,%s\n", regname(r), regname(w)));
}

/* --------------------------------------------------------------------- */

define_insn(load_int, load_RxR)
{
	int r = rreg_int(2);
	int w = wreg_int(0);

	OUT = 0x8B;
	OUT = 0x00|(w<<3)|r;
	if (r == REG_esp) {
		OUT = 0x20|REG_esp;
	}

	debug(("movl (%s),%s\n", regname(r), regname(w)));
}

define_insn(load_float, fload_RxR)
{
	int r = rreg_int(2);

	wreg_float(0);

	OUT = 0xD9;
	OUT = 0x00|r;

	debug(("fld (%s)\n", regname(r)));
}

define_insn(load_double, floadl_RxR)
{
	int r = rreg_int(2);

	wreg_double(0);

	OUT = 0xDD;
	OUT = 0x00|r;

	debug(("fldl (%s)\n", regname(r)));
}

define_insn(store_int, store_xRR)
{
	int r = rreg_int(2);
	int w = rreg_int(1);

	OUT = 0x89;
	OUT = 0x00|(r<<3)|w;
	if (w == REG_esp) {
		OUT = 0x20|REG_esp;
	}

	debug(("movl %s,(%s)\n", regname(r), regname(w)));
}

define_insn(store_float, fstore_RxR)
{
	int w = rreg_int(1);

	rreg_float(2);

	OUT = 0xD9;
	OUT = 0x18|w;

	debug(("fstp (%s)\n", regname(w)));
}

define_insn(store_double, fstorel_RxR)
{
	int w = rreg_int(1);

	rreg_double(2);

	OUT = 0xDD;
	OUT = 0x18|w;

	debug(("fstlp (%s)\n", regname(w)));
}

/* --------------------------------------------------------------------- */

define_insn(cmp_int, cmp_xRR)
{
	int r1 = rreg_int(1);
	int r2 = rreg_int(2);

	OUT = 0x39;
	OUT = 0xC0|(r2<<3)|r1;

	debug(("cmpl %s,%s\n", regname(r2), regname(r1)));
}

/* --------------------------------------------------------------------- */

define_insn(cvt_int_float, cvtif_RxR)
{
	int r = rslot_int(2);

	wreg_float(0);

	OUT = 0xDB;
	OUT = 0x80|REG_ebp;
	LOUT = r;

	debug(("fild %d(ebp)\n", r));
}

define_insn(cvt_int_double, cvtid_RxR)
{
	int r = rslot_int(2);

	wreg_double(0);

	OUT = 0xDB;
	OUT = 0x80|REG_ebp;
	LOUT = r;

	debug(("fild %d(ebp)\n", r));
}

define_insn(cvt_long_float, cvtlf_RxR)
{
	int r = rslot_long(2);

	wreg_float(0);

	OUT = 0xDF;
	OUT = 0xA8|REG_ebp;
	LOUT = r;

	debug(("fildll %d(ebp)\n", r));
}

define_insn(cvt_long_double, cvtld_RxR)
{
	int r = rslot_long(2);

	wreg_double(0);

	OUT = 0xDF;
	OUT = 0xA8|REG_ebp;
	LOUT = r;

	debug(("fildll %d(ebp)\n", r));
}

define_insn(cvt_float_double, cvtfd_RxR)
{
	int o = rslot_float(2);

	wreg_double(0);

	OUT = 0xD9;
	OUT = 0x80|REG_ebp;
	LOUT = o;

	debug(("fld %d(ebp)\n", o));
}

define_insn(cvt_double_float, cvtdf_RxR)
{
	int o = rslot_double(2);

	wreg_float(0);

	OUT = 0xDD;
	OUT = 0x80|REG_ebp;
	LOUT = o;

	debug(("fldl %d(ebp)\n", o));
}

/* --------------------------------------------------------------------- */

define_insn(build_key, set_word_xxC)
{
	jint val = const_int(2);

	LOUT = val;

	debug((".word %08x\n", val));
}

define_insn(build_code_ref, set_wordpc_xxC)
{
	label* l = const_label(2);

	l->type |= Llong|Labsolute;
	l->at = CODEPC;
	LOUT = 0;
	l->from = CODEPC;
	debug((".word ?\n"));
}

/* --------------------------------------------------------------------- */

define_insn(set_label, set_label_xxC)
{
	label* l = const_label(2);
	l->to = CODEPC;
}

define_insn(branch, branch_xCC)
{
	label* l = const_label(1);
	int bt = const_int(2);

	l->type |= Llong|Lrelative;
	switch (bt) {
	case ba:
		OUT = 0xE9;
		l->at = CODEPC;
		LOUT = 0;
		l->from = CODEPC;
		debug(("jmpl ?\n"));
		break;
	case beq:
		OUT = 0x0F;
		OUT = 0x84;
		l->at = CODEPC;
		LOUT = 0;
		l->from = CODEPC;
		debug(("je ?\n"));
		break;
	case bne:
		OUT = 0x0F;
		OUT = 0x85;
		l->at = CODEPC;
		LOUT = 0;
		l->from = CODEPC;
		debug(("jne ?\n"));
		break;
	case blt:
		OUT = 0x0F;
		OUT = 0x8C;
		l->at = CODEPC;
		LOUT = 0;
		l->from = CODEPC;
		debug(("jlt ?\n"));
		break;
	case ble:
		OUT = 0x0F;
		OUT = 0x8E;
		l->at = CODEPC;
		LOUT = 0;
		l->from = CODEPC;
		debug(("jle ?\n"));
		break;
	case bgt:
		OUT = 0x0F;
		OUT = 0x8F;
		l->at = CODEPC;
		LOUT = 0;
		l->from = CODEPC;
		debug(("jgt ?\n"));
		break;
	case bge:
		OUT = 0x0F;
		OUT = 0x8D;
		l->at = CODEPC;
		LOUT = 0;
		l->from = CODEPC;
		debug(("jge ?\n"));
		break;
	case bult:
		OUT = 0x0F;
		OUT = 0x82;
		l->at = CODEPC;
		LOUT = 0;
		l->from = CODEPC;
		debug(("jult ?\n"));
		break;
	case bugt:
		OUT = 0x0F;
		OUT = 0x87;
		l->at = CODEPC;
		LOUT = 0;
		l->from = CODEPC;
		debug(("jugt ?\n"));
		break;
	default:
		ABORT();
	}
}

define_insn(branch_indirect, branch_indirect_xRC)
{
	int r = rreg_int(1);
	assert(const_int(2) == ba);

	OUT = 0xFF;
	OUT = 0xE0|r;

	debug(("jmp (%s)\n", regname(r)));
}

define_insn(call_ref, call_xCC)
{
	label* l = const_label(1);
	assert(const_int(2) == ba);

#if defined(KAFFE_PROFILER)
	if (profFlag && !(l->type & Lnoprofile)) {
		/*  don't profile call_soft */
		profiler_start(globalMethod->totalChildrenClicks, 1);
	}
#endif

	OUT = 0xE8;
	l->type |= Llong|Lrelative;
	l->at = CODEPC;
	LOUT = 0;
	l->from = CODEPC;

	debug(("call ?\n"));

#if defined(KAFFE_PROFILER)
	if (profFlag && !(l->type & Lnoprofile)) {
		/*  don't profile call_soft */
		profiler_end(globalMethod->totalChildrenClicks, 1);
	}
#endif
}

define_insn(call, call_xRC)
{
	int r = rreg_int(1);
	assert(const_int(2) == ba);

#if defined(KAFFE_PROFILER)
	if (profFlag) {
		profiler_start(globalMethod->totalChildrenClicks, 1);
	}
#endif

	OUT = 0xFF;
	OUT = 0xD0|r;

	debug(("call %s\n", regname(r)));

#if defined(KAFFE_PROFILER)
	if (profFlag) {
		profiler_end(globalMethod->totalChildrenClicks, 1);
	}
#endif
}

define_insn(call_indirect_const, call_ind_xCC)
{
	int m = const_int(1);
	assert(const_int(2) == ba);

#if defined(KAFFE_PROFILER)
	if (profFlag) {
		profiler_start(globalMethod->totalChildrenClicks, 1);
	}
#endif

	WOUT = 0x15FF;
	LOUT = m;

	debug(("call *%x\n", m));

#if defined(KAFFE_PROFILER)
	if (profFlag) {
		profiler_end(globalMethod->totalChildrenClicks, 1);
	}
#endif
}

define_insn(push_int, push_xRC)
{
	int r = rreg_int(1);

	OUT = 0xFF;
	OUT = 0xF0|r;

	debug(("pushl %s\n", regname(r)));
}

define_insn(push_float, fpush_xRC)
{
	int r = rreg_int(1);	/* Move the float into a register */

	OUT = 0xFF;
	OUT = 0xF0|r;

	debug(("pushl %s\n", regname(r)));
}

define_insn(push_double, fpushl_xRC)
{
	int o = rslot_double(1);

	OUT = 0xFF;
	OUT = 0xB0|REG_ebp;
	LOUT = o+4;

	debug(("pushl %d(ebp)\n", (o+4)));

	OUT = 0xFF;
	OUT = 0xB0|REG_ebp;
	LOUT = o;

	debug(("pushl %d(ebp)\n", o));
}

define_insn(popargs, popargs_xxC)
{
	int o = const_int(2);
	o *= 4;

	OUT = 0x81;
	OUT = 0xC0|REG_esp;
	LOUT = o;

	debug(("addl %d,esp\n", o));
}

define_insn(return_int, return_Rxx)
{
	forceRegister(seq_dst(s), REG_eax, Rint);
}

define_insn(return_long, returnl_Rxx)
{
	forceRegister(seq_dst(s), REG_eax, Rint);
	forceRegister(seq_dst(s)+1, REG_edx, Rint);
}

define_insn(return_float, freturn_Rxx)
{
	forceRegister(seq_dst(s), REG_flt0, Rfloat);
}

define_insn(return_double, freturnl_Rxx)
{
	forceRegister(seq_dst(s), REG_dbl0, Rdouble);
}

define_insn(returnarg_int, returnarg_xxR)
{
	int r;

	r = rreg_int(2);
	do_move_int(REG_eax, r);
}

define_insn(returnarg_long, returnargl_xxR)
{
	SlotInfo* r;
	int r1;
	int r2;

	r = seq_slot(s, 2);
	r1 = _slowSlotRegister(r, Rint, rread);
	r2 = _slowSlotRegister(r+1, Rint, rread);

	/* Return long is a bit complicated since part of the source may
	 * be the destination.
	 */
	if (REG_eax != r2) {
		do_move_int(REG_eax, r1);
		do_move_int(REG_edx, r2);
	}
	else if (REG_edx != r1) {
		do_move_int(REG_edx, r2);
		do_move_int(REG_eax, r1);
	}
	else {
		/* r1 == REG_edx && r2 == REG_eax - swap */
		OUT = 0x87;
		OUT = 0xC0|r1<<3|r2;
	}
}

define_insn(returnarg_float, freturnarg_xxR)
{
	/* Force value into float register */
	rreg_float(2);
}

define_insn(returnarg_double, freturnargl_xxR)
{
	/* Force value into double register */
	rreg_double(2);
}

/* --------------------------------------------------------------------- */

define_insn(add_int_const, add_RRC)
{
	int rw;
	int v;

	check_reg_01();

	v = const_int(2);
	rw = rwreg_int(0);

	OUT = 0x81;
        OUT = 0xC0|rw;
	LOUT = v;

	debug(("addl #%d,%s\n", v, regname(rw)));
}

define_insn(sub_int_const, sub_RRC)
{
	int rw;
	int v;

	check_reg_01();

	v = const_int(2);
	rw = rwreg_int(0);

	OUT = 0x81;
        OUT = 0xE8|rw;
	LOUT = v;

	debug(("subl #%d,%s\n", v, regname(rw)));
}

define_insn(load_offset_int, load_RRC)
{
	int v = const_int(2);
	int r = rreg_int(1);
	int w = wreg_int(0);

	assert(r != REG_esp);
	OUT = 0x8B;
	OUT = 0x80|(w<<3)|r;
	LOUT = v;

	debug(("movl %d(%s),%s\n", v, regname(r), regname(w)));
}

define_insn(load_byte, loadb_RxR)
{
	int r = rreg_int(2);
	int w = wreg_int(0);

	OUT = 0x0F;
	OUT = 0xBE;
	OUT = 0x00|(w<<3)|r;
	if (r == REG_esp) {
		OUT = 0x20|REG_esp;
	}

	debug(("movsb (%s),%s\n", regname(r), regname(w)));
}

define_insn(load_char, loadc_RxR)
{
	int r = rreg_int(2);
	int w = wreg_int(0);

	OUT = 0x0F;
	OUT = 0xB7;
	OUT = 0x00|(w<<3)|r;
	if (r == REG_esp) {
		OUT = 0x20|REG_esp;
	}

	debug(("movzw (%s),%s\n", regname(r), regname(w)));
}

define_insn(load_short, loads_RxR)
{
	int r = rreg_int(2);
	int w = wreg_int(0);

	OUT = 0x0F;
	OUT = 0xBF;
	OUT = 0x00|(w<<3)|r;
	if (r == REG_esp) {
		OUT = 0x20|REG_esp;
	}

	debug(("movsw (%s),%s\n", regname(r), regname(w)));
}

define_insn(store_offset_int, store_xRRC)
{
	int v;
	int r1;
	int r0;

	v = const_int(2);
	r0 = rreg_int(0);
	r1 = rreg_int(1);

	assert(r0 != REG_esp);
	OUT = 0x89;
	OUT = 0x80|(r0<<3)|r1;
	LOUT = v;

	debug(("movl %s,%d(%s)\n", regname(r0), v, regname(r1)));
}

define_insn(store_byte, storeb_xRR)
{
	int r;
	int w;

	/* Can only store accumulators as bytes */
	r = rreg_int(2);
	if (r == REG_edi || r == REG_esi) {
		do_force_move_int(REG_ebx, r, 2);
	}
	w = rreg_int(1);

	OUT = 0x88;
	OUT = 0x00|(r<<3)|w;
	if (w == REG_esp) {
		OUT = 0x20|REG_esp;
	}

	debug(("movb %s,(%s)\n", regname(r), regname(w)));
}

define_insn(store_short, stores_xRR)
{
	int r = rreg_int(2);
	int w = rreg_int(1);

	OUT = 0x66;
	OUT = 0x89;
	OUT = 0x00|(r<<3)|w;
	if (w == REG_esp) {
		OUT = 0x20|REG_esp;
	}

	debug(("movw %s,(%s)\n", regname(r), regname(w)));
}

define_insn(cmp_int_const, cmp_xRC)
{
	int r1 = rreg_int(1);
	int v = const_int(2);

	OUT = 0x81;
        OUT = 0xF8|r1;
	LOUT = v;

	debug(("cmpl #%d,%s\n", v, regname(r1)));
}

define_insn(push_int_const, push_xCC)
{
	int v = const_int(1);

	OUT = 0x68;
	LOUT = v;

	debug(("pushl #%d\n", v));
}

define_insn(lshl_int_const, lshl_RRC)
{
	int rw;
	int v;

	check_reg_01();

	rw = rreg_int(0);
	v = const_int(2);

	OUT = 0xC1;
        OUT = 0xE0|rw;
	OUT = v;

	debug(("shll #%d,%s\n", v, regname(rw)));
}

/* --------------------------------------------------------------------- */

void
kill_readonce_register (SlotInfo *s)
{
DBG(REGFORCE,
    dprintf ("kill_readonce_register(%s)\n", regname(s->regno));
    )
	if (((reginfo[s->regno].ctype & Rdouble) && (s->regno == REG_dbl0)) ||
	    ((reginfo[s->regno].ctype & Rfloat) && (s->regno == REG_flt0))) {
	    	OUT = 0xDD;
		OUT = 0xD8;

		debug (("fstp %%st(0)\n"));
	}
}