jit3-m68k.def

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	}
	else {
		op_tst_a(r);
	}
}

define_insn(cmp_ref, cmpr_xRR)
{
	int r1 = rreg_ref(1);
	int r2 = rreg_ref(2);

	op_cmpal_aa(r2, r1);
}

#if !defined(HAVE_NO_SWAP_ANY)
define_insn(swap_any, swap_RxR)
{
	int r1, r2, type = 0;

	if (slotInRegister(2, Rref)) {
		r2 = rwreg_ref(2);
		type |= 2;
	}
	else {
		r2 = rwreg_int(2);
	}

	if (slotInRegister(0, Rref)) {
		r1 = rwreg_ref(0);
		type |= 1;
	}
	else {
		r1 = rwreg_int(0);
	}

	switch (type) {
	case 0:
		op_exg_dd(r1, r2);
		break;
	case 3:
		op_exg_aa(r1, r2);
		break;
	case 2:
		op_exg_da(r1, r2);
		break;
	case 1:
		op_exg_da(r2, r1);
		break;
	default:
		abort();
	}
}
#endif

/* --------------------------------------------------------------------- */

define_insn(load_int, loadi_RxR)
{
	int r = rreg_ref(2);
	int w = wreg_int(0);

	op_movel_Id(r, w);
}

define_insn(load_offset_int, loadi_RRC)
{
	int o = const_int(2);
	int r = rreg_ref(1);
	int w = wreg_int(0);

	op_movel_od(r, o, w);
}

define_insn(load_ref, loadr_RxR)
{
	int r = rreg_ref(2);
	int w = wreg_ref(0);

	op_moveal_Ia(r, w);
}

define_insn(load_offset_ref, loadr_RRC)
{
	int o = const_int(2);
	int r = rreg_ref(1);
	int w = wreg_ref(0);

	assert(o >= -0x8000 && o < 0x8000);
	op_moveal_oa(r, o, w);
}

define_insn(load_float, loadf_RxR)
{
	int r = rreg_ref(2);
	int w = wreg_float(0);

	op_fsmoves_If(r, w);
}

define_insn(load_double, loadd_RxR)
{
	int r = rreg_ref(2);
	int w = wreg_double(0);

	op_fdmoved_If(r, w);
}

define_insn(load_byte, loadb_RxR)
{
	int r = rreg_ref(2);
	int w = wreg_int(0);

	op_moveb_Id(r, w);
	op_extbl_d(w);
}

define_insn(load_char, loadc_RxR)
{
	int r = rreg_ref(2);
	int w = wreg_int(0);

	op_clrl_d(w);
	op_movew_Id(r, w);
}

define_insn(load_short, loads_RxR)
{
	int r = rreg_ref(2);
	int w = wreg_int(0);

	op_movew_Id(r, w);
	op_extwl_d(w);
}

define_insn(store_int, storei_xRR)
{
	int r = rreg_int(2);
	int w = rreg_ref(1);

	op_movel_dI(r, w);
}

define_insn(store_offset_int, storei_xRRC)
{
	int o = const_int(2);
	int w = rreg_ref(1);
	int r = rreg_int(0);

	assert(o >= -0x8000 && o < 0x8000);
	op_movel_do(r, w, o);
}

define_insn(store_ref, storer_xRR)
{
	int r = rreg_ref(2);
	int w = rreg_ref(1);

	op_movel_aI(r, w);
}

define_insn(store_offset_ref, storer_xRRC)
{
	int o = const_int(2);
	int w = rreg_ref(1);
	int r = rreg_ref(0);

	assert(o >= -0x8000 && o < 0x8000);
	op_movel_ao(r, w, o);
}

define_insn(store_float, storef_xRR)
{
	int r = rreg_float(2);
	int w = rreg_ref(1);

	op_fmoves_fI(r, w);
}

define_insn(store_double, stored_xRR)
{
	int r = rreg_double(2);
	int w = rreg_ref(1);

	op_fmoved_fI(r, w);
}

define_insn(store_byte, storeb_xRR)
{
	int r = rreg_int(2);
	int w = rreg_ref(1);

	op_moveb_dI(r, w);
}

define_insn(store_short, stores_xRR)
{
	int r = rreg_int(2);
	int w = rreg_ref(1);

	op_movew_dI(r, w);
}

/* --------------------------------------------------------------------- */

define_insn(cvt_int_byte, cvtib_RxR)
{
	int rw = rwreg_int(0);

	assert(rreg_int(2) == rw);

	op_extbl_d(rw);
}

define_insn(cvt_int_short, cvtis_RxR)
{
	int rw = rwreg_int(0);

	assert(rreg_int(2) == rw);

	op_extwl_d(rw);
}

define_insn(cvt_int_float, cvtif_RxR)
{
	int r = rreg_int(2);
	int w = wreg_float(0);

	op_fsmovel_df(r, w);
}

define_insn(cvt_int_double, cvtid_RxR)
{
	int r = rreg_int(2);
	int w = wreg_double(0);

	op_fdmovel_df(r, w);
}

define_insn(cvt_float_double, cvtfd_RxR)
{
	int r = rreg_float(2);
	int w = wreg_double(0);

	if (r != w) {
		op_fdmovex_ff(r, w);
	}
}

define_insn(cvt_double_float, cvtdf_RxR)
{
	int r = rreg_double(2);
	int w = wreg_float(0);

	if (is_68040) {
		op_fsmovex_ff(r, w);
	}
	else {
		/* FIXME -- implement something to return a scratch
		   register.  Until then, arbitrarily kill d0.  */
		clobberRegister(REG_d0);
		op_fmoves_fd(r, REG_d0);
		op_fsmoves_df(REG_d0, w);
	}
}

/* --------------------------------------------------------------------- */

define_insn(build_key, set_word_xxC)
{
	jint val = const_int(2);

	debug((".long %08x\n", val));
	LOUT = val;
}

define_insn(build_code_ref, set_wordpc_xxC)
{
	label* l = const_label(2);

	l->type |= Labsolute | Llong;
	l->at = CODEPC;
	l->from = 0;

	debug((".long ?\n"));
	LOUT = 0;
}

/* --------------------------------------------------------------------- */

define_insn(set_label, set_label_xxC)
{
	label* l = const_label(2);

	l->to = CODEPC;
}

define_insn(branch, branch_xCC)
{
	label* l = const_label(1);
	int bt = const_int(2);

#if defined(HAVE_NO_LONG_BRANCHES)
	l->type |= Llong16 | Lrelative | Lrangecheck;
	l->at = CODEPC+2;
	l->from = CODEPC+2;

	switch (bt) {
	case ba:
		op_bra_16(0);
		break;
	case beq:
		op_beq_16(0);
		break;
	case bne:
		op_bne_16(0);
		break;
	case blt:
		op_blt_16(0);
		break;
	case ble:
		op_ble_16(0);
		break;
	case bgt:
		op_bgt_16(0);
		break;
	case bge:
		op_bge_16(0);
		break;
	case bult:
		op_blo_16(0);
		break;
	default:
		abort();
	}
#else
	l->type |= Llong | Lrelative | Lrangecheck;
	l->at = CODEPC+2;
	l->from = CODEPC+2;

	switch (bt) {
	case ba:
		op_bra_32(0);
		break;
	case beq:
		op_beq_32(0);
		break;
	case bne:
		op_bne_32(0);
		break;
	case blt:
		op_blt_32(0);
		break;
	case ble:
		op_ble_32(0);
		break;
	case bgt:
		op_bgt_32(0);
		break;
	case bge:
		op_bge_32(0);
		break;
	case bult:
		op_blo_32(0);
		break;
	default:
		abort();
	}
#endif
}

define_insn(branch_indirect, branch_indirect_xRC)
{
	int r = rreg_ref(1);
	assert(const_int(2) == ba);

	op_jmp_I(r);
}

define_insn(call_ref, call_xCC)
{
        label* l = const_label(1);
        assert(const_int(2) == ba);

	l->type |= Labsolute | Llong;
	l->at = CODEPC+2;
	l->from = CODEPC+2;

	op_jsr_32(0);
}

define_insn(call, call_xRC)
{
	int r = rreg_ref(1);
	assert(const_int(2) == ba);

	op_jsr_I(r);
}

define_insn(ret, ret_xxx)
{
	op_rts();
}

static void
m68k_pusharg_single(sequence *s)
{
	int r;

	if (slotInRegister(1, Rint)) {
		r = rreg_int(1);
		op_movel_dp(r, REG_sp);
	}
	else if (slotInRegister(1, Rref)) {
		r = rreg_ref(1);
		op_movel_ap(r, REG_sp);
	}
	else {
		r = rslot_int(1);
		op_movel_op(REG_fp, r, REG_sp);
	}
}

define_insn(pusharg_int_const, pushi_xCC)
{
	int o = const_int(1);

	op_movel_ip(o, REG_sp);
}


define_insn(pusharg_int, pushi_xRC)
{
	m68k_pusharg_single(s);
}

define_insn(pusharg_ref_const, pushr_xCC)
{
	int o = const_int(1);

	op_movel_ip(o, REG_sp);
}

define_insn(push_ref, pushr_xRC)
{
	m68k_pusharg_single(s);
}

define_insn(push_float, pushf_xRC)
{
	int r;

	if (slotInRegister(1, Rfloat)) {
		r = rreg_float(1);
		op_fmoves_fp(r, REG_sp);
	}
	else {
		r = rslot_float(1);
		op_movel_op(REG_fp, r, REG_sp);
	}
}

define_insn(push_double, pushd_xRC)
{
	int r = rreg_double(1);

	op_fmoved_fp(r, REG_sp);
}

define_insn(popargs, popargs_xxC)
{
	int o = const_int(2) * 4;

	if (o < 0) {
		abort();
	}
	else if (o > 0) {
		if (o <= 0x8) {
			op_addql_ia(o, REG_sp);
		}
#if !defined(HAVE_NO_ADDAW)
		else if (o < 0x8000) {
			op_addaw_ia(o, REG_sp);
		}
#endif
		else {
			op_addal_ia(o, REG_sp);
		}
	}
}

define_insn(return_int, returni_Rxx)
{
	forceRegister(seq_dst(s), REG_d0, Rint);
}

define_insn(return_ref, returnr_Rxx)
{
	if (M68K_RETURN_REF == REG_a0) {
		forceRegister(seq_dst(s), REG_a0, Rref);
	}
	else {
		forceRegister(seq_dst(s), REG_d0, Rint);
	}
}

define_insn(return_long, returnl_Rxx)
{
	forceRegister(LSLOT(seq_dst(s)), REG_d1, Rint);
	forceRegister(HSLOT(seq_dst(s)), REG_d0, Rint);
}

define_insn(return_float, returnf_Rxx)
{
	forceRegister(seq_dst(s), REG_fp0, Rfloat);
}

define_insn(return_double, returnd_Rxx)
{
	forceRegister(seq_dst(s), REG_fp0, Rdouble);
}

define_insn(returnarg_int, returnargi_xxR)
{
	int r;

	if (slotInRegister(2, Rint)) {
		r = rreg_int(2);
		if (r != REG_d0) {
			op_movel_dd(r, REG_d0);
		}
	}
	else {
		r = rslot_int(2);
		assert(r >= -0x8000 && r < 0x8000);
		op_movel_od(REG_fp, r, REG_d0);
	}
}

define_insn(returnarg_ref, returnargr_xxR)
{
	int r;

	if (slotInRegister(2, Rref)) {
		r = rreg_ref(2);
		if (M68K_RETURN_REF == REG_a0 && r != REG_a0) {
			op_moveal_aa(r, REG_a0);
			r = REG_a0;
		}
	}
	else {
		r = rslot_ref(2);
		assert(r >= -0x8000 && r < 0x8000);
		if (M68K_RETURN_REF == REG_a0) {
			op_moveal_oa(REG_fp, r, REG_a0);
			r = REG_a0;
		}
		else {
			op_movel_od(REG_fp, r, REG_d0);
			r = REG_d0;
		}
	}

	if (r != REG_d0) {
		op_movel_ad(r, REG_d0);
	}
}

define_insn(returnarg_long, returnargl_xxR)
{
	REGSLOT *r;
	int rl, rh;

	r = seq_slot(s, 2);

	if (_slotInRegister(LSLOT(r), Rint)) {
		rl = _slowSlotRegister(LSLOT(r), Rint, rread);
	}
	else {
		rl = slowSlotOffset(LSLOT(r), Rint, rread);
		op_movel_od(REG_fp, rl, REG_d1);
		rl = REG_d1;
	}

	if (_slotInRegister(HSLOT(r), Rint)) {
		rh = _slowSlotRegister(HSLOT(r), Rint, rread);
	}
	else {
		rh = slowSlotOffset(HSLOT(r), Rint, rread);
		op_movel_od(REG_fp, rh, REG_d0);
		rh = REG_d0;
	}

	/* Return long is a bit complicated since part of the source may
	   be the destination.  */
	if (rl == REG_d0 && rh == REG_d1) {
#if defined(HAVE_NO_EXG)
		op_movel_da(REG_d1, REG_a0);
		op_movel_dd(REG_d0, REG_d1);
		op_movel_ad(REG_a0, REG_d0);
#else
		op_exg_dd(rl, rh);
#endif
	}
	else {
		if (rh == REG_d1) {
			op_movel_dd(rh, REG_d0);
		}
		if (rl != REG_d1) {
			op_movel_dd(rl, REG_d1);
		}
		if (rh != REG_d0 && rh != REG_d1) {
			op_movel_dd(rh, REG_d0);
		}
	}
}

define_insn(returnarg_float, returnargf_xxR)
{
	int r;

	if (slotInRegister(2, Rfloat)) {
		r = rreg_float(2);
		if (r != REG_fp0)
			op_fsmovex_ff(r, REG_fp0);
	}
	else {
		r = rslot_float(2);
		assert(r >= -0x8000 && r < 0x8000);
		op_fsmoves_of(REG_fp, r, REG_fp0);
	}
}

define_insn(returnarg_double, returnargd_xxR)
{
	int r;

	if (slotInRegister(2, Rdouble)) {
		r = rreg_double(2);
		if (r != REG_fp0)
			op_fdmovex_ff(r, REG_fp0);
	}
	else {
		r = rslot_double(2);
		assert(r >= -0x8000 && r < 0x8000);
		op_fdmoved_of(REG_fp, r, REG_fp0);
	}
}