jit-m68k.def

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static inline void
op_subql_id(int imm, int dst)
{
	debug(("subql #%d, %s\n", imm, regname(dst)));
	assert(imm >= 1 && imm <= 8);
	assert_dreg(dst);
	WOUT = 0x5180 | ((imm & 7) << 9) | (MODE_d << 3) | dst;
}

static inline void
op_subxl_dd(int src, int dst)
{
	debug(("subxl %s, %s\n", regname(src), regname(dst)));
	assert_dreg(src);
	assert_dreg(dst);
	WOUT = 0x9180 | (dst << 9) | src;
}

static inline void
op_tst_a(int src)
{
	debug(("tst %s\n", regname(src)));
	assert_areg(src);
	WOUT = 0x4A80 | (MODE_a << 3) | (src & 7);
}

static inline void
op_tst_d(int src)
{
	debug(("tst %s\n", regname(src)));
	assert_dreg(src);
	WOUT = 0x4A80 | (MODE_d << 3) | (src & 7);
}

static inline void
op_unlk_a(int areg)
{
	debug(("unlk %s\n", regname(areg)));
	assert_areg(areg);
	WOUT = 0x4E58 | (areg & 7);
}

/* --------------------------------------------------------------------- */

static inline void
_op_fop_ff(int src, int dst, int opmode)
{
	assert_freg(src);
	assert_freg(dst);
	WOUT = 0xF000 | (COPROCID << 9);
	WOUT = ((src & 7) << 10) | ((dst & 7) << 7) | opmode;
}

static inline void
op_fsaddx_ff(int src, int dst)
{
	debug(("fsaddx %s, %s\n", regname(src), regname(dst)));
	_op_fop_ff(src, dst, 0x22 | OPMODE_s);
}

static inline void
op_fdaddx_ff(int src, int dst)
{
	debug(("fdaddx %s, %s\n", regname(src), regname(dst)));
	_op_fop_ff(src, dst, 0x22 | OPMODE_d);
}

static inline void
op_fsdivx_ff(int src, int dst)
{
	debug(("fsdivx %s, %s\n", regname(src), regname(dst)));
	_op_fop_ff(src, dst,  0x20 | OPMODE_s);
}

static inline void
op_fddivx_ff(int src, int dst)
{
	debug(("fddivx %s, %s\n", regname(src), regname(dst)));
	_op_fop_ff(src, dst,  0x20 | OPMODE_d);
}

static inline void
op_fmoves_fI(int src, int base)
{
	debug(("fmoves %s, (%s)\n", regname(src), regname(base)));
	assert_freg(src);
	assert_areg(base);
	WOUT = 0xF000 | (COPROCID << 9) | (MODE_ind << 3) | (base & 7);
	WOUT = 0x6400 | ((src & 7) << 7);
}

static inline void
op_fmoves_fp(int src, int base)
{
	debug(("fmoves %s, -(%s)\n", regname(src), regname(base)));
	assert_freg(src);
	assert_areg(base);
	WOUT = 0xF000 | (COPROCID << 9) | (MODE_predec << 3) | (base & 7);
	WOUT = 0x6400 | ((src & 7) << 7);
}

static inline void
op_fmoves_fo(int src, int base, int disp)
{
	debug(("fmoves %s, %d(%s)\n", regname(src), disp, regname(base)));
	assert_freg(src);
	assert_areg(base);
	assert_s16(disp);
	WOUT = 0xF000 | (COPROCID << 9) | (MODE_inddisp << 3) | (base & 7);
	WOUT = 0x6400 | ((src & 7) << 7);
	WOUT = disp;
}

static inline void
op_fmoves_fd(int src, int dst)
{
	debug(("fmoves %s, %s\n", regname(src), regname(dst)));
	assert_freg(src);
	assert_dreg(dst);
	WOUT = 0xF000 | (COPROCID << 9) | (MODE_d << 3) | (dst & 7);
	WOUT = 0x6400 | ((src & 7) << 7);
}

static inline void
op_fmoved_fI(int src, int base)
{
	debug(("fmoved %s, (%s)\n", regname(src), regname(base)));
	assert_freg(src);
	assert_areg(base);
	WOUT = 0xF000 | (COPROCID << 9) | (MODE_ind << 3) | (base & 7);
	WOUT = 0x7400 | ((src & 7) << 7);
}

static inline void
op_fmoved_fp(int src, int base)
{
	debug(("fmoved %s, -(%s)\n", regname(src), regname(base)));
	assert_freg(src);
	assert_areg(base);
	WOUT = 0xF000 | (COPROCID << 9) | (MODE_predec << 3) | (base & 7);
	WOUT = 0x7400 | ((src & 7) << 7);
}

static inline void
op_fmoved_fo(int src, int base, int disp)
{
	debug(("fmoved %s, %d(%s)\n", regname(src), disp, regname(base)));
	assert_freg(src);
	assert_areg(base);
	assert_s16(disp);
	WOUT = 0xF000 | (COPROCID << 9) | (MODE_inddisp << 3) | (base & 7);
	WOUT = 0x7400 | ((src & 7) << 7);
	WOUT = disp;
}

static inline void
op_fsmoves_df(int src, int dst)
{
	debug(("fsmoves %s, %s\n", regname(src), regname(dst)));
 	assert_dreg(src);
	assert_freg(dst);
	WOUT = 0xF000 | (COPROCID << 9) | (MODE_d << 3) | (src & 7);
	WOUT = 0x4400 | ((dst & 7) << 7) | OPMODE_s;
}

static inline void
op_fsmoves_If(int base, int dst)
{
	debug(("fsmoves (%s), %s\n", regname(base), regname(dst)));
 	assert_areg(base);
	assert_freg(dst);
	WOUT = 0xF000 | (COPROCID << 9) | (MODE_ind << 3) | (base & 7);
	WOUT = 0x4400 | ((dst & 7) << 7) | OPMODE_s;
}

static inline void
op_fdmoved_If(int base, int dst)
{
	debug(("fdmoved (%s), %s\n", regname(base), regname(dst)));
 	assert_areg(base);
	assert_freg(dst);
	WOUT = 0xF000 | (COPROCID << 9) | (MODE_ind << 3) | (base & 7);
	WOUT = 0x5400 | ((dst & 7) << 7) | OPMODE_d;
}

static inline void
op_fsmoves_of(int base, int disp, int dst)
{
	debug(("fsmoves %d(%s), %s\n", disp, regname(base), regname(dst)));
 	assert_areg(base);
	assert_s16(disp);
	assert_freg(dst);
	WOUT = 0xF000 | (COPROCID << 9) | (MODE_inddisp << 3) | (base & 7);
	WOUT = 0x4400 | ((dst & 7) << 7) | OPMODE_s;
	WOUT = disp;
}

static inline void
op_fdmoved_of(int base, int disp, int dst)
{
	debug(("fdmoved %d(%s), %s\n", disp, regname(base), regname(dst)));
 	assert_areg(base);
	assert_s16(disp);
	assert_freg(dst);
	WOUT = 0xF000 | (COPROCID << 9) | (MODE_inddisp << 3) | (base & 7);
	WOUT = 0x5400 | ((dst & 7) << 7) | OPMODE_d;
	WOUT = disp;
}

static inline void
op_fsmovel_df(int src, int dst)
{
	debug(("fsmovel %s, %s\n", regname(src), regname(dst)));
 	assert_dreg(src);
	assert_freg(dst);
	WOUT = 0xF000 | (COPROCID << 9) | (MODE_d << 3) | (src & 7);
	WOUT = 0x4000 | ((dst & 7) << 7) | OPMODE_s;
}

static inline void
op_fdmovel_df(int src, int dst)
{
	debug(("fdmovel %s, %s\n", regname(src), regname(dst)));
 	assert_dreg(src);
	assert_freg(dst);
	WOUT = 0xF000 | (COPROCID << 9) | (MODE_d << 3) | (src & 7);
	WOUT = 0x4000 | ((dst & 7) << 7) | OPMODE_d;
}

static inline void
op_fsmovex_ff(int src, int dst)
{
	debug(("fsmovex %s, %s\n", regname(src), regname(dst)));
	assert_freg(src);
	assert_freg(dst);
	WOUT = 0xF000 | (COPROCID << 9); 
	WOUT = ((src & 7) << 10) | ((dst & 7) << 7) | OPMODE_s;
}

static inline void
op_fdmovex_ff(int src, int dst)
{
	debug(("fdmovex %s, %s\n", regname(src), regname(dst)));
	assert_freg(src);
	assert_freg(dst);
	WOUT = 0xF000 | (COPROCID << 9); 
	WOUT = ((src & 7) << 10) | ((dst & 7) << 7) | OPMODE_d;
}

static inline void
op_fmovemx_ro(int mask, int base, int disp)
{
	debug(("fmovemx 0x%02x, %d(%s)\n", mask, disp, regname(base)));
	assert_s16(disp);
	assert_areg(base);
	WOUT = 0xF000 | (COPROCID << 9) | (MODE_inddisp << 3) | (base & 7);
	WOUT = 0xD000 | mask;
}

static inline void
op_fmovemx_or(int base, int disp, int mask)
{
	debug(("fmovemx %d(%s), 0x%02x\n", disp, regname(base), mask));
	assert_s16(disp);
	assert_areg(base);
	WOUT = 0xF000 | (COPROCID << 9) | (MODE_inddisp << 3) | (base & 7);
	WOUT = 0xE000 | mask;
}

static inline void
op_fsmulx_ff(int src, int dst)
{
	debug(("fsmulx %s, %s\n", regname(src), regname(dst)));
	_op_fop_ff(src, dst,  0x23 | OPMODE_s);
}

static inline void
op_fdmulx_ff(int src, int dst)
{
	debug(("fdmulx %s, %s\n", regname(src), regname(dst)));
	_op_fop_ff(src, dst,  0x23 | OPMODE_d);
}

static inline void
op_fsnegx_ff(int src, int dst)
{
	debug(("fsnegx %s, %s\n", regname(src), regname(dst)));
	_op_fop_ff(src, dst,  0x1A | OPMODE_s);
}

static inline void
op_fdnegx_ff(int src, int dst)
{
	debug(("fdnegx %s, %s\n", regname(src), regname(dst)));
	_op_fop_ff(src, dst,  0x1A | OPMODE_d);
}

static inline void
op_fremx_ff(int src, int dst)
{
	debug(("fremx %s, %s\n", regname(src), regname(dst)));
	_op_fop_ff(src, dst, 0x25);
}

static inline void
op_fssubx_ff(int src, int dst)
{
	debug(("fssubx %s, %s\n", regname(src), regname(dst)));
	_op_fop_ff(src, dst,  0x28 | OPMODE_s);
}

static inline void
op_fdsubx_ff(int src, int dst)
{
	debug(("fdsubx %s, %s\n", regname(src), regname(dst)));
	_op_fop_ff(src, dst,  0x28 | OPMODE_d);
}


/* --------------------------------------------------------------------- */

define_insn(unimplemented, unimplemented)
{
	ABORT();
}

define_insn(nop, nop)
{
	op_nop();
}

/* --------------------------------------------------------------------- */

define_insn(prologue, prologue_xxC)
{
	Method* meth = const_method(2);
	int framesize;

#ifdef KAFFE_VMDEBUG
	if (jit_debug) {
		printf("\n%s.%s %s\n", meth->class->name->data,
			meth->name->data, METHOD_SIGD(meth));
	}
#endif

	/* Work out size of stack frame */
	framesize = (maxLocal - maxArgs + maxStack + maxTemp) * SLOTSIZE;
	op_linkw_ai(REG_fp, -framesize);
}

define_insn(epilogue, epilogue_xxx)
{
	setEpilogueLabel ((uintp)CODEPC);

	op_unlk_a(REG_fp);
	op_rts();
}

define_insn(eprologue, eprologue_xxx)
{
	int framesize = (maxLocal - maxArgs + maxStack + maxTemp) * SLOTSIZE;

	/* Be careful not to dealocate our current frame even for
	   an instant.  */
	op_moveal_aa(REG_fp, REG_a0);
	op_subaw_ia(framesize, REG_a0);
	op_moveal_aa(REG_a0, REG_sp);
}

/* --------------------------------------------------------------------- */

define_insn(spill_int, spilli_RCx)
{
	int r = sreg_int(0);
	int o = const_int(1);

	op_movel_do(r, REG_fp, o);
}

define_insn(spill_ref, spillr_RCx)
{
	int r = sreg_ref(0);
	int o = const_int(1);

	op_movel_ao(r, REG_fp, o);
}

define_insn(spill_float, spillf_RCx)
{
	int r = sreg_float(0);
	int o = const_int(1);

	op_fmoves_fo(r, REG_fp, o);
}

define_insn(spill_double, spilld_RCx)
{
	int r = sreg_double(0);
	int o = const_int(1);

	op_fmoved_fo(r, REG_fp, o);
}

define_insn(reload_int, reloadi_RCx)
{
	int r = lreg_int(0);
	int o = const_int(1);

	op_movel_od(REG_fp, o, r);
}

define_insn(reload_ref, reloadr_RCx)
{
	int r = lreg_ref(0);
	int o = const_int(1);

	op_moveal_oa(REG_fp, o, r);
}

define_insn(reload_float, reloadf_RCx)
{
	int r = lreg_float(0);
	int o = const_int(1);

	op_fsmoves_of(REG_fp, o, r);
}

define_insn(reload_double, reloadd_RCx)
{
	int r = lreg_double(0);
	int o = const_int(1);

	op_fdmoved_of(REG_fp, o, r);
}

/* --------------------------------------------------------------------- */

define_insn(move_int_const, movei_RxC)
{
	int i = const_int(2);
	int w = wreg_int(0);

	if (i >= -0x80 && i < 0x80)
		op_moveq_id(i, w);
	else
		op_movel_id(i, w);
}

define_insn(move_ref_const, mover_RxC)
{
	int i = const_int(2);
	int w = wreg_ref(0);

	op_moveal_ia(i, w);
}

define_insn(move_label_const, mover_RxL)
{
	label* l = const_label(2);
	int w = wreg_ref(0);

	l->type |= Labsolute | Llong;
	l->at = CODEPC+2;

	op_moveal_ia(0, w);
}

define_insn(move_any, movea_RxR)
{
	int r1, r2;

	/* If the source is already in a register, allocate the destination
	   to the same register type.  Otherwise arbitrarily load as int. */

	if (slotInRegister(2, Rref)) {
		r2 = rreg_ref(2);
		r1 = wreg_ref(0);
		if (r1 != r2) {
			op_moveal_aa(r2, r1);
		}
	}
	else if (slotInRegister(2, Rfloat)) {
		r2 = rreg_float(2);
		r1 = wreg_float(0);
		if (r1 != r2) {
			op_fsmovex_ff(r2, r1);
		}
	}
	else if (slotInRegister(2, Rint)) {
		r2 = rreg_int(2);
		r1 = wreg_int(0);
		if (r1 != r2) {
			op_movel_dd(r2, r1);
		}
	}
	else {
		r2 = rslot_int(2);
		r1 = wreg_int(0);
		op_movel_od(REG_fp, r2, r1);
	}
}

define_insn(move_int, movei_RxR)
{
	int r = rreg_int(2);
	int w = wreg_int(0);

	if (r != w) {
		op_movel_dd(r, w);
	}
}

define_insn(move_ref, mover_RxR)
{
	int r = rreg_ref(2);
	int w = wreg_ref(0);

	if (r != w) {
		op_moveal_aa(r, w);
	}
}

define_insn(move_float, movef_RxR)
{
	int r = rreg_float(2);
	int w = wreg_float(0);

	if (r != w) {
		op_fsmovex_ff(r, w);
	}
}

define_insn(move_double, moved_RxR)
{
	int r = rreg_double(2);
	int w = wreg_double(0);

	if (r != w) {
		op_fdmovex_ff(r, w);
	}
}

/* --------------------------------------------------------------------- */

define_insn(add_int_const, addi_RRC)
{
	int o = const_int(2);
	int rw = rwreg_int(0);

	assert(rreg_int(1) == rw);

	if (o >= 1 && o <= 8) {
		op_addql_id(o, rw);
	}
	else {
		op_addl_id(o, rw);
	}
}

define_insn(add_int, addi_RRR)
{
	int r = rreg_int(2);
	int w = rwreg_int(0);

	assert(rreg_int(1) == w);

	op_addl_dd(r, w);
}

define_insn(adc_int, adci_RRR)
{
	int r = rreg_int(2);
	int w = rwreg_int(0);

	assert(rreg_int(1) == w);

	op_addxl_dd(r, w);
}

define_insn(add_ref_const, addr_RRC)
{
	int o = const_int(2);
	int rw = rwreg_ref(0);

	assert(rreg_ref(1) == rw);

	if (o >= 1 && o <= 8) {
		op_addql_ia(o, rw);
	}
	else if (o >= -0x8000 && o < 0x8000) {
		op_addaw_ia(o, rw);
	}
	else {
		op_addal_ia(o, rw);
	}
}

define_insn(add_ref, addr_RRR)
{
	int r = rreg_int(2);
	int w = rwreg_ref(0);

	assert(rreg_ref(1) == w);

	op_addal_da(r, w);
}

define_insn(add_float, addf_RRR)
{
	int r = rreg_float(2);
	int w = rwreg_float(0);

	assert(rreg_float(1) == w);

	op_fsaddx_ff(r, w);
}

define_insn(add_double, addd_RRR)
{
	int r = rreg_double(2);
	int w = rwreg_double(0);

	assert(rreg_double(1) == w);

	op_fdaddx_ff(r, w);
}

define_insn(sub_int_const, subi_RRC)
{
	int o = const_int(2);
	int rw = rwreg_int(0);

	assert(rreg_int(1) == rw);

	if (o >= 1 && o <= 8) {
		op_subql_id(o, rw);
	}
	else {
		op_subl_id(o, rw);
	}
}

define_insn(sub_int, subi_RRR)
{
	int r = rreg_int(2);
	int w = rwreg_int(0);

	assert(rreg_int(1) == w);

	op_subl_dd(r, w);
}

define_insn(sbc_int, sbci_RRR)
{
	int r = rreg_int(2);
	int w = rwreg_int(0);

	assert(rreg_int(1) == w);

	op_subxl_dd(r, w);
}

define_insn(sub_float, subf_RRR)
{
	int r = rreg_float(2);
	int w = rwreg_float(0);

	assert(rreg_float(1) == w);

	op_fssubx_ff(r, w);
}

define_insn(sub_double, subd_RRR)
{
	int r = rreg_double(2);
	int w = rwreg_double(0);

	assert(rreg_double(1) == w);

	op_fdsubx_ff(r, w);
}

define_insn(neg_int, negi_RxR)
{
	int rw = rwreg_int(0);

	assert(rreg_int(2) == rw);

	op_negl_d(rw);
}

define_insn(ngc_int, ngci_RxR)
{
	int rw = rwreg_int(0);

	assert(rreg_int(2) == rw);

	op_negxl_d(rw);
}

define_insn(neg_float, negf_RxR)
{
	int r = rreg_float(2);
	int w = wreg_float(0);

	op_fsnegx_ff(r, w);
}

define_insn(neg_double, negd_RxR)
{
	int r = rreg_double(2);
	int w = wreg_double(0);

	op_fdnegx_ff(r, w);
}

define_insn(mul_int_const, muli_RRC)
{
	int o = const_int(2);
	int rw = rwreg_int(0);

	assert(rreg_int(1) == rw);

	op_mulsl_id(o, rw);
}

define_insn(mul_int, muli_RRR)
{
	int r = rreg_int(2);
	int w = rwreg_int(0);

	assert(rreg_int(1) == w);

	op_mulsl_dd(r, w);
}

define_insn(mul_float, mulf_RRR)
{
	int r = rreg_float(2);
	int w = rwreg_float(0);

	assert(rreg_float(1) == w);

	op_fsmulx_ff(r, w);
}

define_insn(mul_double, muld_RRR)
{
	int r = rreg_double(2);
	int w = rwreg_double(0);

	assert(rreg_double(1) == w);

	op_fdmulx_ff(r, w);
}

define_insn(div_int, divi_RRR)
{
	int r = rreg_int(2);
	int w = rwreg_int(0);

	assert(rreg_int(1) == w);

	op_divsl_ddd(r, w, w);
}

define_insn(div_float, divf_RRR)
{
	int r = rreg_float(2);
	int w = rwreg_float(0);

	assert(rreg_double(1) == w);

	op_fsdivx_ff(r, w);