jit3-arm.def

kaffe Java 解释器语言,源码,Java的子集系统,开放源代码

	for (i = 0; i < limit; i++) {
		preloadRegister(slot_data(localinfo[i]), Rint /*?*/, R0+i);
	}
#if defined(STACK_LIMIT)
	if (i < 4) {
		preloadRegister(slot_data(stack_limit[0]), Rref, R0+i);
	}
#endif
}

define_insn(exception_prologue, eprologue_xxx)
{
	label* l = const_label(1);

	l->type = Lexception|Labsolute|Lgeneral;

	/* Initially, the FP is set --- see CALL_KAFFE_EXCEPTION
	 * We must restore the SP and we must do so in a way that never 
	 * frees anything on the stack.  We use IP as a temp register.
	 */
	op_mov(IP, FP);
	op_sub_c(IP, IP, (REGISTERS_SAVED * SLOTSIZE), 0);
	l->at = (uintp)CODEPC;
	op_sub_const(SP,IP,0); /* Framesize is filled in by Lframe */
	//
	// The following opcodes re-establisht the CONSTPOOL_BASE
	// registers. This is filled it in my Lexception.
	// There should be no space between this first mov_c
	// and the previous sub_const.
	//
	op_mov_c(CONSTPOOL_BASE, 0, 0);
	op_add_c(CONSTPOOL_BASE, CONSTPOOL_BASE, 0, 24);
	op_add_c(CONSTPOOL_BASE, CONSTPOOL_BASE, 0, 16);
	op_add_c(CONSTPOOL_BASE, CONSTPOOL_BASE, 0, 8);

}

define_insn(epilogue, epilogue_xxx)
{
	setEpilogueLabel ((uintp)CODEPC);

	/* Should restore floating point state here !!! F4-F7 */

	debug((DBOUT,"maxStack = %d, maxLocal = %d, maxTemp = %d\n", maxStack, maxLocal, maxTemp));
	/*
	 * Pushed as
	 * FP	-> FP
	 * IP 	-> SP (actually, SP -> SP)
	 * LR   -> PC
	 * Rest are caller-saves
	 */
	op_pop_epilogue(FP,BFP|BSP|BPC|BR4|BR5|BR6|BR7|BR8|BR9|BR10);
}

#if defined(STACK_LIMIT)
define_insn(check_stack_limit, check_stack_limit_xRC)
{
        int r = rreg_int(1);
        label* l = const_label(2);

	op_cmp(SP, r);
	op_branch(CC_HI, 8);

	l->type = Lconstant | Labsolute | Loffset12;
        l->at = CODEPC;

	op_load_offset(r, CONSTPOOL_BASE, -128);
	debug((DBOUT,"load_label_const r%d, ?\n", r));

	op_mov(LR, PC);
	op_mov(PC, r);
}
#endif

/* --------------------------------------------------------------------- */

define_insn(spill_int, spill_Rxx)
{
	int r = sreg_int(0);
	int o = const_int(1);

	assert(__I12const_rangecheck(o));
	op_store_offset(r, FP, o);

	debug((DBOUT,"spill_int %d, [FP, %d]\n", r, o));
}

define_insn(spill_float, fspill_Rxx)
{
	int r = sreg_float(0);
	int o = const_int(1);

	assert(__I10const_rangecheck(o));
	assert( (o & 0x3) == 0);
	op_fstore_offset(r, FP, o >> 2);

	debug((DBOUT,"spill_float %d, [FP, %d]\n", r, o));
}

define_insn(spill_double, fspilll_Rxx)
{
	int r = sreg_double(0);
	int o = const_int(1);

	assert(__I10const_rangecheck(o));
	assert( (o & 0x3) == 0);
	op_fstorel_offset(r, FP, o >> 2);

	debug((DBOUT,"spill_double %d, [FP, %d]\n", r, o));
}

define_insn(reload_int, reload_Rxx)
{
	int r = lreg_int(0);
	int o = const_int(1);

	assert(__I12const_rangecheck(o));
	op_load_offset(r, FP, o);

	debug((DBOUT,"reload_int %d, [FP, %d]\n", r, o));
}

define_insn(reload_float, freload_Rxx)
{
	int r = lreg_float(0);
	int o = const_int(1);

	assert(__I10const_rangecheck(o));
	assert( (o & 0x3) == 0);
	op_fload_offset(r, FP, o >> 2);

	debug((DBOUT,"reload_float %d, [FP, %d]\n", r, o));
}

define_insn(reload_double, freloadl_Rxx)
{
	int r = lreg_double(0);
	int o = const_int(1);

	assert(__I10const_rangecheck(o));
	assert( (o & 0x3) == 0);
	op_floadl_offset(r, FP, o >> 2);

	debug((DBOUT,"reload_double %d, [FP, %d]\n", r, o));
}

void
movereg_RR(int toreg, int fromreg)
{
	op_mov(toreg, fromreg);
}

/* --------------------------------------------------------------------- */

define_insn(move_int_const, move_RxC)
{
	int val = const_int(2);
	int w = wreg_int(0);
	int shift = 0;
	int sval = val;

	while (shift < 32) {
		/* Does sval fit in 8 bits after shifted by `shift' bits?
		 * NB: op_mov_c requires that the 8-bit immediate 
		 * be ROTATED to the right, hence the (32 - shift) % 32.
		 */
		if ((sval & 0xFFFFFF00) == 0) {
			op_mov_c(w, sval, (32 - shift) % 32);

			debug((DBOUT,"move_int_const %d, %d (0x%x) via shift (%d, %d)\n", w, val, val, sval, shift));

			return;
		}
		else if ((sval & 0x000000FF) != 0) {
			/* Can't handle this kind of number encoding */
			break;
		}
		sval = sval >> 2;
		shift += 2;
	}

	/* Fail to encode in a short fashion - fall back on a long one */
	//
	// Notice that this shouldn't occur any more due to the
	// range check -- we should fall back on the constant pool.
	//
	op_mov_c(w, val & 0x000000FF, 0);
	op_add_c(w, w, (val >> 8) & 0x000000FF, 24);
	op_add_c(w, w, (val >> 16) & 0x000000FF, 16);
	op_add_c(w, w, (val >> 24) & 0x000000FF, 8);

	debug((DBOUT,"move_int_const %d, %d (0x%x)\n", w, val, val));
}

//
// This doesn't get used as much as it used to
// since most constants are stored in the
// constant pool and referenced via load_constpool_<type>
//
// However, this is still needed to assemble a 32-bit
// constant inline.
//
define_insn(move_label_const, move_RxL)
{
	label* l = const_label(2);
	int w = wreg_int(0);

	l->type |= Llong8x8x8x8|Labsolute;
	l->at = CODEPC;
	/* Assemble constants with a move and four shifted adds */
	op_mov_c(w, 0, 0);
	op_add_c(w, w, 0, 24);
	op_add_c(w, w, 0, 16);
	op_add_c(w, w, 0, 8);
	debug((DBOUT,"move_label_const %d, ?\n", w));
}

define_insn(load_constpool_int, ld_RxL)
{
	label* l = const_label(2);
	int w = wreg_int(0);
	l->type = Lconstant | Labsolute | Loffset12;
	l->at = CODEPC;
	//
	// Initially set the offset to be negative, and thus
	// force the MEM_SUBOFF flag to be set..
	//
	op_load_offset(w, CONSTPOOL_BASE, -128);
	debug((DBOUT,"load_label_const %d, ?\n", w));
}

define_insn(load_constpool_float, fld_RxL)
{
	label* l = const_label(2);
	int w = wreg_float(0);
	l->type = Lconstant | Labsolute | Lfoffset8;
	l->at = CODEPC;
	//
	// Initially set the offset to be negative, and thus
	// force the MEM_SUBOFF flag to be set..
	//
	op_fload_offset(w, CONSTPOOL_BASE, -128);
	debug((DBOUT,"load_label_const %d, ?\n", w));
}

define_insn(load_constpool_double, fldl_RxL)
{
	label* l = const_label(2);
	int w = wreg_double(0);
	l->type = Lconstant | Labsolute | Lfoffset8;
	l->at = CODEPC;
	//
	// Initially set the offset to be negative, and thus
	// force the MEM_SUBOFF flag to be set..
	//
	op_floadl_offset(w, CONSTPOOL_BASE, -128);
	debug((DBOUT,"load_label_const %d, ?\n", w));
}

define_insn(move_int, move_RxR)
{
	int r = rreg_int(2);
	int w = wreg_int(0);

	op_mov(w, r);

	debug((DBOUT,"move_int %d, %d\n", w, r));
}

define_insn(move_float, fmove_RxR)
{
	int r = rreg_float(2);
	int w = wreg_float(0);

	op_fmov(w, r);

	debug((DBOUT,"move_float %d, %d\n", w, r));
}

define_insn(move_float_const, fmove_RxC)
{
	float o = const_float(2);
	int w = wreg_float(0);

	int r = 0;

	if ( o == 0.0 ) {
	    r = 0x8 | 0;
	} else if (o == 1.0) {
	    r = 0x8 | 1;
	} else if (o == 2.0) {
	    r = 0x8 | 2;
	} else if (o == 3.0) {
	    r = 0x8 | 3;
	} else if (o == 4.0) {
	    r = 0x8 | 4;
	} else if (o == 5.0) {
	    r = 0x8 | 5;
	} else if (o == 0.5) {
	    r = 0x8 | 6;
	} else if (o == 10.0) {
	    r = 0x8 | 7;
	} else {
	    ABORT();
	}

	op_fmov(w, r);

	debug((DBOUT,"move_float_const %d, %f(0x%x)\n", w, o,r ));
}

define_insn(move_double, fmovel_RxR)
{
	int r = rreg_double(2);
	int w = wreg_double(0);

	op_fmovl(w, r);

	debug((DBOUT,"move_double %d, %d\n", w, r));
}

define_insn(move_double_const, fmovel_RxC)
{
	double o = const_double(2);
	int w = wreg_double(0);

	int r = 0;

	if ( o == 0.0 ) {
	    r = 0x8 | 0;
	} else if (o == 1.0) {
	    r = 0x8 | 1;
	} else if (o == 2.0) {
	    r = 0x8 | 2;
	} else if (o == 3.0) {
	    r = 0x8 | 3;
	} else if (o == 4.0) {
	    r = 0x8 | 4;
	} else if (o == 5.0) {
	    r = 0x8 | 5;
	} else if (o == 0.5) {
	    r = 0x8 | 6;
	} else if (o == 10.0) {
	    r = 0x8 | 7;
	} else {
	    ABORT();
	}

	op_fmovl(w, r);

	debug((DBOUT,"move_double_const %d, %f(0x%x)\n", w, o,r ));
}


/* --------------------------------------------------------------------- */

define_insn(add_int, add_RRR)
{
	int r2 = rreg_int(2);
	int r1 = rreg_int(1);
	int w = wreg_int(0);

	op_add(w, r1, r2);

	debug((DBOUT,"add_int %d, %d, %d\n", w, r1, r2));
}

define_insn(add_int_const, add_RRC)
{
	int o = const_int(2);
	int r1 = rreg_int(1);
	int w = wreg_int(0);

	if ( o < 0 ) {
		op_sub_const(w, r1, -o);
		debug((DBOUT,"sub_int_const %d, %d, %d\n", w, r1, -o));
	} else {
		op_add_const(w, r1, o);
		debug((DBOUT,"add_int_const %d, %d, %d\n", w, r1, o));
	}
}

define_insn(adc_int, adc_RRR)
{
	int r2 = rreg_int(2);
	int r1 = rreg_int(1);
	int w = wreg_int(0);

	op_adc(w, r1, r2);

	debug((DBOUT,"adc_int %d, %d, %d\n", w, r1, r2));
}

define_insn(add_float, fadd_RRR)
{
	int r2 = rreg_float(2);
	int r1 = rreg_float(1);
	int w = wreg_float(0);

	op_fadd(w, r1, r2);

	debug((DBOUT,"add_float %d, %d, %d\n", w, r1, r2));
}

define_insn(add_double, faddl_RRR)
{
	int r2 = rreg_double(2);
	int r1 = rreg_double(1);
	int w = wreg_double(0);

	op_faddl(w, r1, r2);

	debug((DBOUT,"add_double %d, %d, %d\n", w, r1, r2));
}

define_insn(sub_int, sub_RRR)
{
	int r2 = rreg_int(2);
	int r1 = rreg_int(1);
	int w = wreg_int(0);

	op_sub(w, r1, r2);

	debug((DBOUT,"sub_int %d, %d, %d\n", w, r1, r2));
}

define_insn(sub_int_const, sub_RRC)
{
	int o = const_int(2);
	int r1 = rreg_int(1);
	int w = wreg_int(0);

	if ( o < 0 ) {
		op_add_const(w, r1, -o);
		debug((DBOUT,"add_int_const %d, %d, %d\n", w, r1, -o));
	} else {
		op_sub_const(w, r1, o);
		debug((DBOUT,"add_int_const %d, %d, %d\n", w, r1, o));
	}

	debug((DBOUT,"sub_int_const %d, %d, %d\n", w, r1, 0));
}

define_insn(sbc_int, sbc_RRR)
{
	int r2 = rreg_int(2);
	int r1 = rreg_int(1);
	int w = wreg_int(0);

	op_sbc(w, r1, r2);

	debug((DBOUT,"sbc_int %d, %d, %d\n", w, r1, r2));
}

define_insn(sub_float, fsub_RRR)
{
	int r2 = rreg_float(2);
	int r1 = rreg_float(1);
	int w = wreg_float(0);

	op_fsub(w, r1, r2);

	debug((DBOUT,"sub_float %d, %d, %d\n", w, r1, r2));
}

define_insn(sub_double, fsubl_RRR)
{
	int r2 = rreg_double(2);
	int r1 = rreg_double(1);
	int w = wreg_double(0);

	op_fsubl(w, r1, r2);

	debug((DBOUT,"sub_double %d, %d, %d\n", w, r1, r2));
}

define_insn(mul_int, mul_RRR)
{
	int r2 = rreg_int(2);
	int r1 = rreg_int(1);
	int w = wreg_int(0);

	op_mul(w, r1, r2);

	debug((DBOUT,"mul_int %d, %d, %d\n", w, r1, r2));
}

define_insn(mul_float, fmul_RRR)
{
	int r2 = rreg_float(2);
	int r1 = rreg_float(1);
	int w = wreg_float(0);

	op_fmul(w, r1, r2);

	debug((DBOUT,"mul_float %d, %d, %d\n", w, r1, r2));
}

define_insn(mul_double, fmull_RRR)
{
	int r2 = rreg_double(2);
	int r1 = rreg_double(1);
	int w = wreg_double(0);

	op_fmull(w, r1, r2);

	debug((DBOUT,"mul_double %d, %d, %d\n", w, r1, r2));
}

define_insn(div_float, fdiv_RRR)
{
	int r2 = rreg_float(2);
	int r1 = rreg_float(1);
	int w = wreg_float(0);

	op_fdiv(w, r1, r2);

	debug((DBOUT,"div_float %d, %d, %d\n", w, r1, r2));
}

define_insn(div_double, fdivl_RRR)
{
	int r2 = rreg_double(2);
	int r1 = rreg_double(1);
	int w = wreg_double(0);

	op_fdivl(w, r1, r2);

	debug((DBOUT,"div_double %d, %d, %d\n", w, r1, r2));
}

/* --------------------------------------------------------------------- */

define_insn(and_int, and_RRR)
{
	int r2 = rreg_int(2);
	int r1 = rreg_int(1);
	int w = wreg_int(0);

	op_and(w, r1, r2);

	debug((DBOUT,"and_int %d, %d, %d\n", w, r1, r2));
}

define_insn(and_int_const, and_RRC)
{
	int o = const_int(2);
	int r1 = rreg_int(1);
	int w = wreg_int(0);

	op_and_const(w, r1, o);

	debug((DBOUT,"and_int_const %d, %d, %d\n", w, r1, 0));
}


define_insn(or_int, or_RRR)
{
	int r2 = rreg_int(2);
	int r1 = rreg_int(1);
	int w = wreg_int(0);

	op_or(w, r1, r2);

	debug((DBOUT,"or_int %d, %d, %d\n", w, r1, r2));
}

define_insn(xor_int, xor_RRR)
{
	int r2 = rreg_int(2);
	int r1 = rreg_int(1);
	int w = wreg_int(0);

	op_eor(w, r1, r2);

	debug((DBOUT,"xor_int %d, %d, %d\n", w, r1, r2));
}

define_insn(ashr_int, ashr_RRR)
{
	int r2 = rreg_int(2);
	int r1 = rreg_int(1);
	int w = wreg_int(0);

	op_ashr(w, r1, r2);

	debug((DBOUT,"ashr_int %d, %d, %d\n", w, r1, r2));
}

define_insn(lshr_int, lshr_RRR)
{
	int r2 = rreg_int(2);
	int r1 = rreg_int(1);
	int w = wreg_int(0);

	op_lshr(w, r1, r2);

	debug((DBOUT,"lshr_int %d, %d, %d\n", w, r1, r2));
}

define_insn(lshl_int, lshl_RRR)
{
	int r2 = rreg_int(2);
	int r1 = rreg_int(1);
	int w = wreg_int(0);

	op_lshl(w, r1, r2);

	debug((DBOUT,"lshl_int %d, %d, %d\n", w, r1, r2));
}

//
// Although this definition looks find to me, it appears to cause
// errors. I've decoded the instructions by hand and they appear
// to match, but I'm not loosing more sleep over this - dirk.
//
define_insn(lshl_int_const, lshl_RRC)
{
	int w = wreg_int(0);
	int r = rreg_int(1);
	int v = const_int(2);

	op_lshl_const(w, r, v);

	debug((DBOUT,"shll %d, %d, LSL %d\n", w, r, v));
}


/* --------------------------------------------------------------------- */
//
// Load/store offset

define_insn(load_offset_int, load_RRC)
{
	int v = const_int(2);
	int r = rreg_int(1);
	int w = wreg_int(0);

	op_load_offset(w, r, v);
	debug((DBOUT,"ld %d, [%d+%d]\n", w, r, v));
}

define_insn(store_offset_int, store_RRC)
{
	int v = const_int(2);
	int r0 = rreg_int(0);
	int r1 = rreg_int(1);