debug.c

GDB Remote Stub Backend for debugging an embedded ARM system via JTAG common hardware debug interfac

/*
 *  Copyright (C) 2004 Tobias Lorenz
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

/* debugging and register functions */

#include <stdio.h>
#include <stdlib.h>

#include "jtag.h"
#include "debug.h"
#include "ice.h"


regs_type arm_regs;
unsigned long debug_status;


void debug_exec_begin(void)
{
    /* select Scan Chain 1 */
    sc_select(SC_Debug);

    /* select Intest */
    jtag_instruction(JTAG_INTEST, NULL, 0);
}

unsigned long debug_exec(unsigned long cmd, unsigned long data, int type)
{
    /* allows for an automatic swapping around command/data */
    unsigned long my_data[3];
    int temp;

    if (type == DEBUG_SPEED_SHORT) {
    	printf("short access not fully tested\n");
    	/* do a short (only 33 bit) access */
    	my_data[0] = 0;
    	my_data[1] = 0;

	/* need to reverse the bit order for the command */
	for (temp = 1; temp < 32; temp ++) {
	    if (cmd & (1 << temp)) {
	    	/* bit set */
		my_data[0] |= (1 << (33 - temp));
	    }
	}
	
	if (cmd & 1) {
	    /* bit set */
	    my_data[2] = 1;
	}

	jtag_dreg(my_data, 33);
    } else {
	/* do a long (67 bit) access */
	my_data[0] = data;
	my_data[1] = 0; 
	my_data[2] = 0;

	if (type == SYSTEM_SPEED)
	    my_data[1] = 1 << 2;

	/* need to reverse the bit order for the command */
	for (temp = 3; temp < 32; temp ++) {
	    if (cmd & (1 << temp)) {
		/* bit set */
		my_data[1] |= (1 << (34 - temp));
	    }
	}
	
	for (temp = 0; temp < 3; temp ++) {
	    if (cmd & (1 << temp)) {
		/* bit set */
		my_data[2] |= (1 << (2 - temp));
	    }
	}
	
	jtag_dreg(my_data, 67);
    }

    /* return the data value */
    return my_data[0];
}

void debug_save_regs(void)
{
    unsigned long temp;

    /* Check current DEBUG state */
    debug_status = ice_register(ICE_Debug_status, 0, 0);
    if (debug_status & ICE_DSR_DBGACK) {
        printf("System HALTED in ");

	if (debug_status & ICE_DSR_ITBIT) {
    	    printf("Thumb State\n");
	} else {
    	    printf("32bit State\n");
	}
    } else {
        printf("System NOT HALTED\n");
    }

    /* disable interrupts */
    ice_register(ICE_Debug_control, ICE_DCR_DBGRQ|ICE_DCR_INTDIS, 1);

    /* save pc and r0 */
    debug_exec_begin();
    if (debug_status & ICE_DSR_ITBIT) {
    	/* send Thumb sequence */
	debug_exec(0x60006000, 0, DEBUG_SPEED);	/* STR r0, [r0]	- Save R0 before use */
    	debug_exec(0x46784678, 0, DEBUG_SPEED);	/* MOV r0, PC 	- Copy PC into R0 */
    	debug_exec(0x60006000, 0, DEBUG_SPEED);	/* STR r0, [r0] - Now save the PC in R0 */

	arm_regs.r[0]=
    	debug_exec(0x47784778, 0, DEBUG_SPEED);	/* BX PC	- Jump into ARM state */

	debug_exec(0xe1a00000, 0, DEBUG_SPEED);	/* NOP */

	arm_regs.pc =
	debug_exec(0xe1a00000, 0, DEBUG_SPEED)	/* NOP		- Read out PC */
	- 12;					/* Correct for delay -12 = (4+2)*2 */
    	printf("Thumb sequence is not tested yet...\n");
    } else {
	/* send 32bit sequence */
	debug_exec(0xe5800000, 0, DEBUG_SPEED);	/* STR r0, [r0]	- Save R0 before use */
	debug_exec(0xe1a0000f, 0, DEBUG_SPEED);	/* MOV r0, PC 	- Copy PC into R0 */
	debug_exec(0xe5800000, 0, DEBUG_SPEED);	/* STR r0, [r0] - Now save the PC in R0 */

	arm_regs.r[0] =
	debug_exec(0xe1a00000, 0, DEBUG_SPEED);	/* NOP		- Read out R0 */

	debug_exec(0xe1a00000, 0, DEBUG_SPEED);	/* NOP */

	arm_regs.pc =
	debug_exec(0xe1a00000, 0, DEBUG_SPEED)	/* NOP		- Read out PC */
	- 24;					/* Correct for delay -24 = (4+2)*4 */
    }

    /* save r1-r14 */
    debug_exec(0xe8807ffe, 0, DEBUG_SPEED);	/* STMIA r0, {r1-r14} */
    debug_exec(0xe1a00000, 0, DEBUG_SPEED);	/* NOP */
    debug_exec(0xe1a00000, 0, DEBUG_SPEED);	/* NOP */
    for (temp = 1; temp <= 14; temp ++)
	arm_regs.r[temp] =
	debug_exec(0xe1a00000, 0, DEBUG_SPEED);	/* NOP */

    /* determine the state of the CPSR register */
    debug_exec(0xe1a00000, 0, DEBUG_SPEED);	/* NOP */
    debug_exec(0xe1a00000, 0, DEBUG_SPEED);	/* NOP */
    debug_exec(0xe10f0000, 0, DEBUG_SPEED);	/* MRS r0, cpsr */
    debug_exec(0xe1a00000, 0, DEBUG_SPEED);	/* NOP */
    debug_exec(0xe1a00000, 0, DEBUG_SPEED);	/* NOP */
    debug_exec(0xe5800000, 0, DEBUG_SPEED);	/* STR r0, [r0]		- Save CPSR to determine current mode */
    debug_exec(0xe1a00000, 0, DEBUG_SPEED);	/* NOP */
    debug_exec(0xe1a00000, 0, DEBUG_SPEED);	/* NOP */
    arm_regs.cpsr =
    debug_exec(0xe1a00000, 0, DEBUG_SPEED);	/* NOP */

    printf("R0: %8.8x   PC: %8.8x   CPSR: %8.8x\n", arm_regs.r[0], arm_regs.pc, arm_regs.cpsr);
}

void debug_restore_regs(void)
{
    unsigned long temp;
    
    /* write CPSR register */
    debug_exec_begin();
    debug_exec(0xe5900000, 0            , DEBUG_SPEED);	/* LDR r0, [r0]		- restore CPSR */
    debug_exec(0xe1a00000, 0            , DEBUG_SPEED);	/* NOP */
    debug_exec(0xe1a00000, 0            , DEBUG_SPEED);	/* NOP */
    debug_exec(0xe1a00000, arm_regs.cpsr, DEBUG_SPEED);	/* NOP 			- scan in value for CPSR */
    debug_exec(0xe12ff000, 0            , DEBUG_SPEED);	/* MSR cpsr, r0	       */
    debug_exec(0xe1a00000, 0            , DEBUG_SPEED);	/* NOP */
    debug_exec(0xe1a00000, 0            , DEBUG_SPEED);	/* NOP */

    /* restore r1-r14 */
    debug_exec(0xe8907ffe, 0, DEBUG_SPEED);	/* LDMIA r0, {r1-r14} */
    debug_exec(0xe1a00000, 0, DEBUG_SPEED);	/* NOP */
    debug_exec(0xe1a00000, 0, DEBUG_SPEED);	/* NOP */
    for (temp = 1; temp <= 14; temp ++)
	debug_exec(0xe1a00000, arm_regs.r[temp], DEBUG_SPEED);

    /* restore pc and r0 */
    if (debug_status & ICE_DSR_ITBIT) {
	/* send Thumb sequence */
	debug_exec(0xe3800001, 0            , DEBUG_SPEED);	/* ORR r0, r0, #1	- add 1 to PC to force thumb */
	debug_exec(0xe12fff11, 0            , DEBUG_SPEED);	/* BX r1		- enter thumb state */
	debug_exec(0xe59f0000, 0            , DEBUG_SPEED);	/* LDR r0, [pc]		- restore R0 */
	debug_exec(0xe1a00000, arm_regs.r[0], DEBUG_SPEED);	/* NOP			- scan in calue for r0 */
	debug_exec(0xe1a00000, arm_regs.pc-8, DEBUG_SPEED);	/* B <pc> - 8		- */
    	printf("Thumb sequence is not tested yet...\n");
    } else {
	/* send 32bit sequence */
	debug_exec(0xe5900000, 0            , DEBUG_SPEED);	/* LDR r0, [r0]		- restore PC */
	debug_exec(0xe1a00000, 0            , DEBUG_SPEED);	/* NOP */
	debug_exec(0xe1a00000, 0            , DEBUG_SPEED);	/* NOP */
	debug_exec(0xe1a00000, arm_regs.pc  , DEBUG_SPEED);	/* NOP 			- scan in value for PC */
	debug_exec(0xe1a0f000, 0            , DEBUG_SPEED);	/* MOV PC, r0		- put r0 into PC */
	debug_exec(0xe1a00000, 0            , DEBUG_SPEED);	/* NOP */
	debug_exec(0xe1a00000, 0            , DEBUG_SPEED);	/* NOP */
	debug_exec(0xe5900000, 0            , DEBUG_SPEED);	/* LDR r0, [r0]		- restore R0 */
	debug_exec(0xe1a00000, 0            , DEBUG_SPEED);	/* NOP */
	debug_exec(0xe1a00000, 0            , DEBUG_SPEED);	/* NOP */
	debug_exec(0xe1a00000, arm_regs.r[0], DEBUG_SPEED);	/* NOP			- scan in value for r0 */
	debug_exec(0xe24ff014, 0            , DEBUG_SPEED);	/* SUB PC, PC, #0x14	- jump back PC */
    }

    /* Return to system speed */
    debug_exec(0xe1a00000, 0, SYSTEM_SPEED);
    jtag_instruction(JTAG_RESTART, NULL, 0);
}

void debug_stop(void)
{
    /* set debug request */
    ice_register(ICE_Debug_control, ICE_DCR_DBGRQ, 1);

    /* wait for DBGACK */
    while (!ice_halted()) usleep(100);

    debug_save_regs();
}

void debug_step(void)
{
    /* disable interrupts and single stepping */
    ice_register(ICE_Debug_control, ICE_DCR_Single_step|ICE_DCR_INTDIS, 1);

    debug_restore_regs();

    /* wait for DBGACK */
    while (!ice_halted()) usleep(100);

    debug_save_regs();
}

void debug_run(void)
{
    /* enable interrupts */
    ice_register(ICE_Debug_control, 0, 1);
    
    debug_restore_regs();
}