i2c8_sim.v

来自「I2c 总线测试程序,经过多次验证的.包括读写模式(第一次上传)」· Verilog 代码 · 共 75 行

module i2c8_sim(SCL8, SDA8);
  inout SCL8, SDA8;
  
  assign (pull1,pull0) SCL8 = 1'b1;
  assign (pull1,pull0) SDA8 = 1'b1;
  
  reg SCL8_M,SDA8_M;
  reg [7:0] wdat8_tmp,rdat8_tmp,wdat8,rdat8;
  reg ack8;
  integer i8;
  reg [7:0] wtreg;
  
  initial
  begin
    wdat8_tmp = 8'hzz;
    rdat8_tmp = 8'h00;
    wdat8 = 8'h00;
    rdat8 = 8'h00;
    ack8 = 1'b0;
    SDA8_M = 1'bz;
    SCL8_M = 1'bz;
    wtreg = 8'b0;
    
    # 10000;
    //-------------------------------------
  repeat(256)
  begin  
    `include "./i2c8/i2c8_start.v"
    
    wdat8 = 8'hD8;
    `include "./i2c8/i2c8_write_byte.v"
    wdat8 = wtreg;
    `include "./i2c8/i2c8_write_byte.v"
    
    wdat8 = wtreg; `include "./i2c8/i2c8_write_byte.v"
    
    `include "./i2c8/i2c8_stop.v"
    wtreg = wtreg + 1;
  end
    //-------------------------------------
    
    `include "./i2c8/i2c8_start.v"
    
    wdat8 = 8'hD8;
    `include "./i2c8/i2c8_write_byte.v"
    wdat8 = 8'h00;
    `include "./i2c8/i2c8_write_byte.v"
    
    `include "./i2c8/i2c8_stop.v"
    
    `include "./i2c8/i2c8_start.v"
    
    wdat8 = 8'hD9;
    `include "./i2c8/i2c8_write_byte.v"
    
    repeat(256)
    begin
      `include "./i2c8/i2c8_read_byte.v"
    end
    
    `include "./i2c8/i2c8_read_last.v"
    
    `include "./i2c8/i2c8_stop.v"
    //-------------------------------------
    
    # 10000; $finish;
  end
  
  assign (strong1,strong0) SCL8 = SCL8_M;
  assign (strong1,strong0) SDA8 = SDA8_M;
  
endmodule