📄 dspbuild1.mdl
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BackgroundColor "white"
DropShadow off
NamePlacement "normal"
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
ShowName on
}
BlockParameterDefaults {
Block {
BlockType Scope
Floating off
ModelBased off
TickLabels "OneTimeTick"
ZoomMode "on"
Grid "on"
TimeRange "auto"
YMin "-5"
YMax "5"
SaveToWorkspace off
SaveName "ScopeData"
LimitDataPoints on
MaxDataPoints "5000"
Decimation "1"
SampleInput off
SampleTime "0"
}
Block {
BlockType "S-Function"
FunctionName "system"
PortCounts "[]"
SFunctionModules "''"
}
Block {
BlockType Step
Time "1"
Before "0"
After "1"
SampleTime "-1"
VectorParams1D on
ZeroCross on
}
}
AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
}
LineDefaults {
FontName "Helvetica"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
System {
Name "dspbuild1"
Location [2, 70, 1022, 704]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
ZoomFactor "100"
ReportName "simulink-default.rpt"
Block {
BlockType Reference
Name "AltBus"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [285, 277, 350, 293]
ForegroundColor "blue"
SourceBlock "bus_alteradspbuilder/AltBus"
SourceType "AltBus AlteraBlockSet"
sgn "Single Bit"
nodetype "Input Port"
bwl "1"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "AltBus"
ppat "E:\\matlab\\DSPBuilder\\DSPBuilder_dspbuild1"
nSgCpl "0"
}
Block {
BlockType Reference
Name "AltBus1"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [1000, 237, 1065, 253]
ForegroundColor "blue"
SourceBlock "bus_alteradspbuilder/AltBus"
SourceType "AltBus AlteraBlockSet"
sgn "Unsigned Integer"
nodetype "Output Port"
bwl "8"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "AltBus1"
ppat "E:\\matlab\\DSPBuilder\\DSPBuilder_dspbuild1"
nSgCpl "0"
}
Block {
BlockType Reference
Name "BusConcatenation"
Ports [2, 1]
Position [835, 226, 940, 264]
ForegroundColor "blue"
SourceBlock "bus_alteradspbuilder/BusConcatenation"
SourceType "Bus Concatenation AlteraBlockSet"
bwl "1"
bwr "7"
blean off
}
Block {
BlockType Reference
Name "BusConversion"
Ports [1, 1]
Position [660, 246, 735, 264]
ForegroundColor "blue"
SourceBlock "bus_alteradspbuilder/BusConversion"
SourceType "SubBus Altera BlockSet"
Inputs "Signed Integer"
bwl "8"
bwr "8"
Outputs "Signed Integer"
obwl "7"
obwr "8"
msb "6"
lsb "0"
rnd off
sat off
}
Block {
BlockType Reference
Name "Delay"
Ports [1, 1]
Position [295, 165, 340, 215]
ForegroundColor "blue"
SourceBlock "store_alteradspbuilder/Delay"
SourceType "Delay AlteraBlockSet"
depth "1"
clken off
MaskValue "1"
}
Block {
BlockType Reference
Name "ExtractBit"
Ports [1, 1]
Position [660, 198, 715, 222]
ForegroundColor "blue"
SourceBlock "bus_alteradspbuilder/ExtractBit"
SourceType "ExtractBit AlteraBlockSet"
bwl "8"
bwr "0"
Outputs "7"
}
Block {
BlockType Reference
Name "IncCount"
Ports [0, 1]
Position [15, 168, 70, 212]
ForegroundColor "blue"
SourceBlock "arithm_alteradspbuilder/Increment\nDecrement"
SourceType "IncDec AlteraBlockSet"
BusType "Signed Integer"
bwl "6"
bwr "4"
direction "Increment"
cst_display "0"
cst "0"
clken off
MaskValue "1"
ntsamp "0"
}
Block {
BlockType Reference
Name "NOT"
Ports [1, 1]
Position [750, 202, 790, 218]
ForegroundColor "blue"
SourceBlock "gate_alteradspbuilder/NOT"
SourceType "LogiBit AlteraBlockSet"
Operator "NOT"
Inputs "2"
}
Block {
BlockType Reference
Name "Product"
Ports [2, 1]
Position [415, 208, 480, 257]
ForegroundColor "blue"
SourceBlock "arithm_alteradspbuilder/Product"
SourceType "Product Altera BlockSet"
pipeline "0"
lpm on
eab off
clken off
MaskValue "1"
}
Block {
BlockType Scope
Name "Scope"
Ports [2]
Position [1100, 236, 1130, 269]
Location [462, 224, 890, 646]
Open off
NumInputPorts "2"
TickLabels "on"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
axes2 "%<SignalLabel>"
}
TimeRange "500"
YMin "-5~-5"
YMax "5~5"
DataFormat "StructureWithTime"
}
Block {
BlockType Reference
Name "SignalCompiler"
Ports []
Position [169, 38, 238, 85]
ForegroundColor "blue"
SourceBlock "ALTELINK/AltLab/SignalCompiler"
SourceType "SignalCompiler"
family "Cyclone"
opt "Speed"
synthtool "Others"
vstim off
SynthAct "None"
workdir "E:\\matlab\\DSPBuilder"
Procetype "prod"
UseReset on
ResetPin "Active High"
ClockPin "Output to Pin"
ClockPeriod "20"
UseSignalTap off
CreatePtfFile on
SignalTapDepth "128"
VerilogSupport on
}
Block {
BlockType Reference
Name "SinLUT"
Ports [1, 1]
Position [135, 168, 220, 212]
ForegroundColor "blue"
SourceBlock "gate_alteradspbuilder/LUT"
SourceType "LUT AlteraBlockSet"
BusType "Signed Integer"
bwl "8"
bwr "0"
bwaddr "6"
MatlabArray "127*sin( [0:2*pi/(2^6):2*pi] )"
LocPin "dspbuild1_SinLUT"
lpm off
modulename "E:\\matlab\\DSPBuilder\\DSPBuilder_dspbuild1\\d"
"spbuild1_SinLUT.lut"
pipeline off
IslibDir "0"
}
Block {
BlockType Reference
Name "SinOut"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [540, 227, 605, 243]
ForegroundColor "blue"
SourceBlock "bus_alteradspbuilder/AltBus"
SourceType "AltBus AlteraBlockSet"
sgn "Signed Integer"
nodetype "Internal Node"
bwl "8"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "SinOut"
ppat "E:\\matlab\\DSPBuilder\\DSPBuilder_dspbuild1"
nSgCpl "0"
}
Block {
BlockType Step
Name "Step"
Position [210, 270, 240, 300]
Time "50"
SampleTime "1"
}
Line {
SrcBlock "IncCount"
SrcPort 1
DstBlock "SinLUT"
DstPort 1
}
Line {
SrcBlock "SinLUT"
SrcPort 1
DstBlock "Delay"
DstPort 1
}
Line {
SrcBlock "AltBus"
SrcPort 1
Points [15, 0]
Branch {
Points [0, -40]
DstBlock "Product"
DstPort 2
}
Branch {
Points [0, 35; 695, 0; 0, -60]
DstBlock "Scope"
DstPort 2
}
}
Line {
SrcBlock "Product"
SrcPort 1
DstBlock "SinOut"
DstPort 1
}
Line {
SrcBlock "Step"
SrcPort 1
DstBlock "AltBus"
DstPort 1
}
Line {
SrcBlock "SinOut"
SrcPort 1
Points [10, 0]
Branch {
Points [0, -25]
DstBlock "ExtractBit"
DstPort 1
}
Branch {
Points [0, 20]
DstBlock "BusConversion"
DstPort 1
}
}
Line {
SrcBlock "ExtractBit"
SrcPort 1
DstBlock "NOT"
DstPort 1
}
Line {
SrcBlock "NOT"
SrcPort 1
Points [10, 0; 0, 25]
DstBlock "BusConcatenation"
DstPort 1
}
Line {
SrcBlock "BusConversion"
SrcPort 1
DstBlock "BusConcatenation"
DstPort 2
}
Line {
SrcBlock "BusConcatenation"
SrcPort 1
DstBlock "AltBus1"
DstPort 1
}
Line {
SrcBlock "AltBus1"
SrcPort 1
DstBlock "Scope"
DstPort 1
}
Line {
SrcBlock "Delay"
SrcPort 1
Points [0, 30]
DstBlock "Product"
DstPort 1
}
Annotation {
Position [883, 400]
}
}
}
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