rem_ans.asm

TI公司TMS320LF240X DSP实现CAN通讯的完整源代码！！！！！用2000系列DSP的同志不下载会后悔

* PROGRAM TO AUTO-ANSWER TO A REMOTE FRAME REQUEST IN 24x/240xA CAN *
* To be used along with REM-REQ.asm								    *
* Reception and transmission by MBX2. Low priority interrupt used 	*

; Transmit acknowledge for MBX2 is set after running this program
; and the message is transmitted.

	.title 		"REM_ANS"  	; Title 
    .include    "240x.h"		; Variable and register declaration
    .include    "vector.h"		; Vector table (takes care of dummy password)
    .global		START

;-----------------------------------------------------------
; Constant definitions
;-----------------------------------------------------------	 

DP_PF1		.set	0E0h	    ; Page 1 of peripheral file (7000h/80h
DP_CAN		.set	0E2h        ; CAN Register (7100h)
DP_CAN2		.set	0E4h        ; CAN RAM (7200h)

;-----------------------------------------------------------------------------
; M A C R O - Definitions
;-----------------------------------------------------------------------------

KICK_DOG	.macro				; Watchdog reset macro
		LDP		#00E0h
		SPLK	#05555h, WDKEY
		SPLK	#0AAAAh, WDKEY
		LDP		#0h
		.endm

;==============================================================================
; M A I N   C O D E  - starts here
;==============================================================================
		.text

START:	KICK_DOG        		; Reset Watchdog counter
		SPLK	#0,60h
		OUT		60h,WSGR		; Set waitstates for external memory (if used)
		LDP		#0E0h
		SPLK	#006Fh, WDCR	; Disable WD 
		SPLK	#0010h,SCSR1	; Enable clock to CAN module (For 240xA only)
				    
		LDP		#225		
		SPLK	#00C0H,MCRB		; Configure CAN pins			
			        
;**************************************************************************
; Enable 1 core interrupt 
;**************************************************************************

		LDPK	#0
		SPLK	#0000000000010000b, IMR	; core interrupt mask register
;			 	 ||||||||||||||||		; Enable INT5 for CAN
;			 	 FEDCBA9876543210 

		SPLK	#000FFh,IFR				; Clear all core interrupt flags
		CLRC	INTM                    ; enable interrupt

		LDP 	#DP_CAN
		SPLK	#1011111111111111b,CANIMR	; Enable all CAN interrupts
		
;**************************************************************************
;******     DISABLE MBX BEFORE WRITING TO MSGID/MSGCTRL OF MBX2  **********
;**************************************************************************	   	

		SPLK	#0000000000000000b,CANMDER 	
;			 	 ||||||||||||||||
;			 	 FEDCBA9876543210
		
;**************************************************************************
;***********                Write CAN Mailboxes                  **********
;**************************************************************************

		LDP		#DP_CAN2
			
		SPLK	#1011111111111111b,CANMSGID2H  
;			 	 ||||||||||||||||
;			 	 FEDCBA9876543210 

;bit 0-12	upper 13 bits of extended identifier
;bit 13		Auto answer mode bit
;bit 14		Acceptance mask enable bit
;bit 15		Identifier extension bit   
			
		SPLK	#1111111111111111b,CANMSGID2L			
;			 	 ||||||||||||||||
;			 	 FEDCBA9876543210

;bit 0-15	lower part of extended identifier

		SPLK	#0000000000001000b,CANMSGCTRL2
;			 	 ||||||||||||||||
;			 	 FEDCBA9876543210

;bit 0-3	Data length code: 1000 = 8 bytes
;bit 4		0: data frame 

        LDP 	#DP_CAN
		SPLK	#0000000100000000b,CANMCR 	; Set CDR bit before writing
;			 	 ||||||||||||||||
;			 	 FEDCBA9876543210 	
        
        LDP		#DP_CAN2
        SPLK	#0BEBEh,CANMBX2A	; Message to transmit
		SPLK	#0BABAh,CANMBX2B
		SPLK	#0DEDEh,CANMBX2C	   	
		SPLK	#0DADAh,CANMBX2D
		
		LDP 	#DP_CAN
		SPLK	#0000000000000000b,CANMCR 	; Clear CDR bit after writing
;			 	 ||||||||||||||||
;			 	 FEDCBA9876543210 
		
;**************************************************************************
;***********    		Enable Mailbox                   		**********
;**************************************************************************

		SPLK	#0000000000000100b,CANMDER 	
;			 	 ||||||||||||||||
;			 	 FEDCBA9876543210

;bit 0-5	Enable  MBX2
;bit 6		MBX2 configured as Transmit MBX

;**************************************************************************
;***********    Bit timing Registers configuration   **********************
;**************************************************************************
		
		SPLK	#0001000000000000b,CANMCR 	
;			 	 ||||||||||||||||
;			 	 FEDCBA9876543210

;bit 12		Change configuration request for write-access to BCR (CCR=1)

W_CCE	BIT		CANGSR,#0Bh	; Wait for Change config Enable
		BCND	W_CCE,NTC	; bit to be set in GSR
         
        ;SPLK	#0000000000000000b,CANBCR2     ; For 1 M bits/s @ 20 MHz CLKOUT
        SPLK	#0000000000000001b,CANBCR2     ; For 1 M bits/s @ 40 MHz CLKOUT
;			 	 ||||||||||||||||
;			     FEDCBA9876543210 

; bit 0-7	Baud rate prescaler	 
; bit 8-15	Reserved
	    
		SPLK	#0000000011111010b,CANBCR1     ; For 1 M bits/s @ 85 % samp. pt
;			 	 ||||||||||||||||
;			  	 FEDCBA9876543210  

; bit 0-2	TSEG2	 
; bit 3-6	TSEG1				
; bit 7		Sample point setting (1: 3 times, 0: once)
; bit 8-9	Synchronization jump width 	
; bit A-F	Reserved 

		SPLK	#0000000000000000b,CANMCR 	
;			  	 ||||||||||||||||
;			  	 FEDCBA9876543210 

;bit 12		Change conf register

W_NCCE	BIT		CANGSR,#0Bh	; Wait for Change config disable
		BCND	W_NCCE,TC
	
ELOOP		B	ELOOP		; Wait for Receive Interrupt

;==================================================================
; ISR used to toggle XF to indicate remote frame was received
;==================================================================

GISR5:		     	

LOOP2 	MAR		*,AR0
		SETC	XF		
		CALL 	DELAY
		CLRC	XF		
		CALL 	DELAY
		B 		LOOP2

DELAY	LAR 	AR0,#0FFFFh
LOOP	RPT 	#080h
		NOP
		BANZ 	LOOP
		RET

GISR1:		RET
GISR2:		RET
GISR3:		RET
GISR4:		RET
GISR6:		RET

PHANTOM 	RET		
		
		.end

; When data in MBX2 is transmitted in response to a "Remote frame request,"
; XF is toggled.  Note that TRS bit is not set for MBX2. The transmission of
; MBX2 data is automatic ,in response to a "Remote frame request."