pwrdown.asm

TI公司TMS320LF240X DSP实现CAN通讯的完整源代码！！！！！用2000系列DSP的同志不下载会后悔

* 		PWRDOWN	 - Demonstrates the powerdown feature of CAN		

* This program puts the CAN module in Low-power mode.

; XF is pulsed slowly after the CAN module comes out of LPM

	.title 		"TXLOOP"  		; Title 
    .include    "240x.h"		; Variable and register declaration
    .include    "vector.h"		; Vector table (takes care of dummy password)
    .global	START
     	
;------------------------------------------------------------------------
; Other constant definitions
;------------------------------------------------------------------------	 
DP_PF1		.set	0E0h	; Page 1 of peripheral file (7000h/80h)E0
DP_CAN		.set	0E2h    ; CAN Registers (7100h)
DP_CAN2		.set	0E4h   	; CAN RAM (7200h)

KICK_DOG	.macro				; Watchdog reset macro
		LDP		#00E0h
		SPLK	#05555h, WDKEY
		SPLK	#0AAAAh, WDKEY
		LDP		#0h
		.endm

		.text

START:	KICK_DOG                ; Reset Watchdog counter
		SPLK	#0,60h
		OUT		60h,WSGR		; Set waitstates for external memory (if used)
		SETC	INTM    		; Disable interrupts
		SPLK	#0000h,IMR		; Mask all core interrupts
		LDP		#0E0h
		SPLK	#006Fh, WDCR	; Disable WD 
		SPLK	#0010h,SCSR1	; Enable clock to CAN module (For 240xA only)				
		    
		LDP		#225		
		SPLK	#00C0H,MCRB		; Configure CAN pins	
		
	    LDP 	#DP_CAN		    ; Enable all CAN interrupts. This is reqd
		SPLK	#03F7Fh,CANIMR	; to poll flags.		

;**************************************************************************
;******     DISABLE MBX BEFORE WRITING TO MSGID/MSGCTRL OF MBX5  **********
;**************************************************************************	 
	
		SPLK	#0000000000000000b,CANMDER   ; Disable all mailboxes
;			 	 ||||||||||||||||	     
;			 	 FEDCBA9876543210	 
	
;**************************************************************************
;***********    Set MSGID/MSGCTRL for transmit mailbox           **********
;**************************************************************************
 
		LDP		#DP_CAN2
				
		SPLK	#1010111000010101b,CANMSGID5H	; Set mailbox 5 ID
;		  	 	 ||||||||||||||||				; XMIT Mailbox
;			 	 FEDCBA9876543210  

;bit 0-12	upper 13 bits of extended identifier
;bit 13		Auto answer mode bit
;bit 14		Acceptance mask enable bit
;bit 15		Identifier extension bit

		SPLK	#1101110000110101b,CANMSGID5L	; AE15 DC35 --> ID	
;			 	 ||||||||||||||||
;			 	 FEDCBA9876543210 

;bit 0-15	lower part of extended identifier
		

		SPLK	#0000000000001000b,CANMSGCTRL5	; 0008
;			 	 ||||||||||||||||
;			 	 FEDCBA9876543210

;bit 0-3	Data length code. 1000 = 8 bytes
;bit 4		0: data frame

		SPLK	#1000000000000000b,CANMSGID0H
		SPLK	#0000000000000001b,CANMSGID0L
		
;**************************************************************************
;******     ENABLE MBX AFTER WRITING TO MSGID/MSGCTRL OF MBX5  **********
;**************************************************************************	 
        
        LDP 	#DP_CAN
 		SPLK	#0000000000100001b,CANMDER 	
;			 	 ||||||||||||||||
;			 	 FEDCBA9876543210

;bit 0-5	enable mailbox 5
                  	
;**************************************************************************
;***********                Write CAN Mailboxes                  **********
;**************************************************************************	
		
		LDP		#DP_CAN2
		SPLK	#00100h,CANMBX5A	; Message to transmit
		SPLK	#00302h,CANMBX5B
		SPLK	#00504h,CANMBX5C	   	
		SPLK	#00706h,CANMBX5D
		
;**************************************************************************
;***********    Bit timing Registers configuration   **********************
;**************************************************************************
		
		LDP 	#DP_CAN	
		SPLK	#0001000000000000b,CANMCR 	
;			 	 ||||||||||||||||
;			 	 FEDCBA9876543210

;bit 12		Change configuration request for write-access to BCR (CCR=1)

W_CCE	BIT		CANGSR,BIT4	; Wait for Change config Enable
		BCND	W_CCE,NTC		; bit to be set in GSR
         
        ;SPLK	#0000000000000000b,CANBCR2     ; For 1 M bits/s @ 20 MHz CLKOUT
        SPLK	#0000000000000001b,CANBCR2     ; For 1 M bits/s @ 40 MHz CLKOUT
;			 	 ||||||||||||||||
;			     FEDCBA9876543210 

; bit 0-7	Baud rate prescaler	 
; bit 8-15	Reserved
	    
		SPLK	#0000000011111010b,CANBCR1     ; For 1 M bits/s @ 85 % samp. pt
;			 	 ||||||||||||||||
;			  	 FEDCBA9876543210  

; bit 0-2	TSEG2	 
; bit 3-6	TSEG1				
; bit 7		Sample point setting (1: 3 times, 0: once)
; bit 8-9	Synchronization jump width 	
; bit A-F	Reserved 

		SPLK	#0000000000000000b,CANMCR 	
;			  	 ||||||||||||||||
;			  	 FEDCBA9876543210 

;bit 12		Change conf register

W_NCCE	BIT		CANGSR,#0Bh	; Wait for Change config disable
		BCND	W_NCCE,TC

;**************************************************************************
;*********** 	TRANSMIT & DRIVE CAN INTO LPM                    **********
;**************************************************************************

TX_LOOP	SPLK	#0080h,CANTCR	; Transmit request for mailbox 5					
		
W_TA	BIT		CANTCR,BIT15	; Wait for transmission acknowledge
		BCND	W_TA,NTC

		SPLK	#8000h,CANTCR	; reset TA 

		SPLK	#0000101000000000b,CANMCR 	; Set PDR & WUBA bits = 1
;			 	 ||||||||||||||||
;			 	 FEDCBA9876543210

W_PDA	BIT		CANGSR,BIT3		; Wait for PDA
		BCND	W_PDA,NTC		; bit to be set in GSR
		
; CAN is now in LPM waiting for some data on the CAN bus to wake it up..

W_PDAe	BIT		CANGSR,BIT3		; Wait for PDA bit to be cleared
		SETC	XF 				; A fast toggling XF bit indicates  
		RPT		#0FFh			; that the module is waiting to be  
		NOP						; pulled out of LPM
		CLRC	XF	
		RPT		#0FFh			 
		NOP	
		BCND	W_PDAe,TC		  
		
LOOP3	
LOOP2 	MAR		*,AR0			; A slowly toggling XF bit indicates
		SETC	XF				; that the module has come out of LPM
		CALL 	DELAY
		CLRC	XF		
		CALL 	DELAY
		B 		LOOP2

DELAY	LAR 	AR0,#0FFFFh
LOOP	RPT 	#080h
		NOP
		BANZ 	LOOP
		RET
		B		LOOP3			; Loop here after exiting LPM
		
GISR1:	
GISR2:	
GISR3:	
GISR4:	
GISR5:	
GISR6:	
PHANTOM:	RET
		.end