rxloop.asm

TI公司TMS320LF240X DSP实现CAN通讯的完整源代码！！！！！用2000系列DSP的同志不下载会后悔

* 		RXLOOP - Transmit loop using Mailbox 2		

* This program RECEIVES data from another CAN module using MAILBOX2
* The number of times data was transmitted is recorded in AR0.	

* A CLKOUT of 40 MHz yields a baud rate of 500 kbits/s.

; XF is pulsed everytime a packet is received

; Last update 12/27/2002	 
    
    .title 		"RXLOOP"  		; Title 
    .include    "240x.h"		; Variable and register declaration
    .include    "vector.h"		; Vector table (takes care of dummy password)
    .global 	START
    
;------------------------------------------------------------------------
; Other constant definitions
;------------------------------------------------------------------------	 
DP_PF1		.set	0E0h	; Page 1 of peripheral file (7000h/80h)E0
DP_CAN		.set	0E2h    ; CAN Registers (7100h)
DP_CAN2		.set	0E4h   	; CAN RAM (7200h)

		.text

START:	SETC	INTM    		; Disable interrupts
		LDP		#0E0h
		SPLK	#006Fh, WDCR	; Disable WD 
		SPLK	#0010h,SCSR1	; Enable clock to CAN module (For 240xA only)				
		LAR		AR0,#0			; AR0 keeps track of the # of receive cycles
		MAR		*,AR0
		    
		            
		LDP		#225		
		SPLK	#00C0H,MCRB		; Configure CAN pins			
                          
        LDP 	#DP_CAN		    ; Enable all CAN interrupts
		SPLK	#03F7Fh,CANIMR			

;**************************************************************************
;******     DISABLE MBX BEFORE WRITING TO MSGID/MSGCTRL OF MBX0  **********
;**************************************************************************	 
	
		SPLK	#0000000000000000b,CANMDER   ; Disable all mailboxes
;			 	 ||||||||||||||||	     
;			 	 FEDCBA9876543210		                                
	                                                   
;**************************************************************************
;***********    Set MSGID/MSGCTRL for transmit mailbox           **********
;**************************************************************************
 
		LDP		#DP_CAN2
				
		SPLK	#1100111000010101b,CANMSGID2H	
;		  	 	 ||||||||||||||||				
;			 	 FEDCBA9876543210  

;bit 0-12	upper 13 bits of extended identifier
;bit 13		Auto answer mode bit
;bit 14		Acceptance mask enable bit
;bit 15		Identifier extension bit

		SPLK	#1101110000110101b,CANMSGID2L	; E15 DC35 --> ID	
;			 	 ||||||||||||||||
;			 	 FEDCBA9876543210 

;bit 0-15	lower part of extended identifier		

;**************************************************************************
;******     ENABLE MBX AFTER WRITING TO MSGID  **********
;**************************************************************************	 
        
        LDP 	#DP_CAN
 		SPLK	#0000000011000100b,CANMDER 	
;			 	 ||||||||||||||||
;			 	 FEDCBA9876543210

;bit 0-5	enable mailbox 0
                  	
;**************************************************************************
;***********    Bit timing Registers configuration   **********************
;**************************************************************************
		
		SPLK	#0001000000000000b,CANMCR 	
;		 	 	 ||||||||||||||||
;		 	 	 FEDCBA9876543210

;bit 12		Change configuration request for write-access to BCR (CCR=1)

W_CCE	BIT		CANGSR,#0Bh	; Wait for Change config Enable
		BCND	W_CCE,NTC	; bit to be set in GSR

		SPLK	#3,CANBCR2     					; For 500 kbits/s @ @ 40 MHz CLKOUT
;			 	 ||||||||||||||||
;			     FEDCBA9876543210 

; bit 0-7	Baud rate prescaler	 
; bit 8-15	Reserved	
	
		
		SPLK	#0000000011110011b,CANBCR1     ; For 500 kbits/s @ 80 % samp. pt
;			 	 ||||||||||||||||
;			  	 FEDCBA9876543210  

; bit 0-2	TSEG2	 
; bit 3-6	TSEG1				
; bit 7		Sample point setting (1: 3 times, 0: once)
; bit 8-9	Synchronization jump width 	
; bit A-F	Reserved 


		SPLK	#0000010000000000b,CANMCR 	
;			  	 ||||||||||||||||
;			  	 FEDCBA9876543210 

;bit 12		Change conf register

W_NCCE	BIT		CANGSR,#0Bh		; Wait for Change config disable
		BCND	W_NCCE,TC
                           
;**************************************************************************
;***********                      RECEIVE                       **********
;**************************************************************************
RX_LOOP	 
		
W_RMP	BIT		CANRCR,BIT6		; Wait for transmission acknowledge
		BCND	W_RMP,NTC
		
		SPLK	#00F0h,CANRCR	; reset RMP
		
		MAR		*+				; Increment receive counter
		SETC	XF 				; A toggling XF bit indicates  
		RPT		#080h			; that data is being received
		NOP						; 
		CLRC	XF				   	       
        
LOOP	B		RX_LOOP			; Execute the receive loop again

GISR1:	RET
GISR2:	RET
GISR3:	RET
GISR4:	RET
GISR5:	RET
GISR6:	RET
PHANTOM:	RET

		.end     

Notes: The transmitting node should transmit with an ID of E15 DC35 @ 500 kbits/s