lptx5pol.asm

TI公司TMS320LF240X DSP实现CAN通讯的完整源代码！！！！！用2000系列DSP的同志不下载会后悔

* 		PROGRAM TO CHECK THE CAN OF 24x/240x DSP	  					*
* 		LPTX5POL - Transmit loop using Mailbox 5 						*
* 	MBX5 used for TRANSMISSION	MBX0 used for RECEPTION					*
* This program TRANSMITS data to another CAN module using MAILBOX5.		*
* ECRX0POL program should be running on the remote CAN module. The 		*
* receiving CAN module,	after receiving the data packets, will echo the *
* same data back to the	transmitting module which then verifies the 	*
* Xmitted and Received data. The program terminates if there is an error*
* Else it loops forever.												*

* COMMENTS : 
; This program, in conjunction with ECRX0POL, provides a quick and easy way
; to determine if two 24x/240x DSPs are able to communicate via the CAN bus. 
; This program does not use any interrupts and employs POLLING. Hence, it
; can be run anywhere in Program memory. 
; This program employs message filtering.
			  
    .title 		"LPTX5POL"  	; Title 
    .include	"240x.h"		; Variable and register declaration 	
	.include    "vector.h"		; Vector table (takes care of dummy password)
	.global		START
	
;-------------------------------------------------------------------
; Other constant definitions
;-------------------------------------------------------------------	 
DP_PF1		.set	0E0h	; Page 1 of peripheral file (7000h/80h)E0
DP_CAN		.set	0E2h    ; CAN Registers (7100h)
DP_CAN2		.set	0E4h   	; CAN RAM (7200h)

KICK_DOG	.macro				; Watchdog reset macro
		LDP		#00E0h
		SPLK	#05555h, WDKEY
		SPLK	#0AAAAh, WDKEY
		LDP		#0h
			.endm

		.text

START:	KICK_DOG
		SPLK	#0,60h
		OUT		60h,WSGR		; Set waitstates for external memory (if used)
		SETC	INTM  			; Disable interrupts
		LDP		#DP_PF1		    ; Set PLL to x4 and enable clock to CAN module
		SPLK	#0010h,SCSR1	; '240xA only - Comment out for '24x
		SPLK	06Fh,WDCR		; Disable watchdog    		
		CALL	AR_INIT    
		LDP		#225		
		SPLK	#00C0H,MCRB		; Configure CAN pins	
	
		LAR		AR7,#300h		; *AR7 keeps track of transmit cycles
		MAR		*,AR7
		SPLK	#0h,*

;**********************************************************************
;**************    Disable all mailboxes	      ********************
;**********************************************************************

		LDP 	#DP_CAN 		 
		        
		SPLK	#1001101011011001b,CANLAM0H ; Set LAM (9AD9 64D2)
		SPLK	#0110010011010010b,CANLAM0L	; 1:don't care
			
		SPLK	#0000000000000000b,CANMDER  ; Disable all mailboxes
;			 	 ||||||||||||||||	     	; Required before writing 
;			 	 FEDCBA9876543210	     	; to MSGID  	

;**********************************************************************
;***********                Write CAN Mailboxes                  ******
;**********************************************************************
; Set MSGIDs for both transmit and receive mailboxes

		LDP		#DP_CAN2				
	    
		SPLK	#1000111000010101b,CANMSGID5H	; Set mailbox 5 ID
;		  	 	 ||||||||||||||||				; XMIT Mailbox
;			 	 FEDCBA9876543210               ; 8E15

;bit 0-12	upper 13 bits of extended identifier
;bit 13		Auto answer mode bit
;bit 14		Acceptance mask enable bit
;bit 15		Identifier extension bit

		SPLK	#1101110000110101b,CANMSGID5L   ; DC35
	
;bit 0-15	lower part of extended identifier  
         
		SPLK	#1100110010010001b,CANMSGID0H	; Set mailbox 0 ID
;		  	 	 ||||||||||||||||			  	; RCV Mailbox
;			 	 FEDCBA9876543210      	        ; CC91
         
        SPLK	#1101100111111001b,CANMSGID0L   ; D9F9
        	
; Write to MSGCTRL register 

		SPLK	#0000000000001000b,CANMSGCTRL5	; 0008
;			 	 ||||||||||||||||
;			 	 FEDCBA9876543210

;bit 0-3	Data length code. 1000 = 8 bytes
;bit 4		0: data frame

;*******************************************************************
;******     ENABLE MBX AFTER WRITING TO MSGID/MSGCTRL     **********
;*******************************************************************
 		
 		LDP 	#DP_CAN	
 		SPLK	#0000000000100001b,CANMDER 	
;			 	 ||||||||||||||||
;			 	 FEDCBA9876543210

;bit 0-5	enable mailboxes 0 & 5 

;*******************************************************************
;***********                Write CAN Mailboxes           **********
;*******************************************************************    
        
        LDP		#DP_CAN2
		SPLK	#00123h,CANMBX5A		; Message to transmit
		SPLK	#04567h,CANMBX5B
		SPLK	#089ABh,CANMBX5C	   	
		SPLK	#0CDEFh,CANMBX5D

;*******************************************************************
;***********  Bit timing registers configuration    ****************
;*******************************************************************
        
        LDP 	#DP_CAN
		SPLK	#0001000000000000b,CANMCR 	
;			 	 ||||||||||||||||
;			 	 FEDCBA9876543210

;bit 12	Change configuration request for write-access to BCR (CCR=1)

W_CCE	BIT		CANGSR,#0Bh			; Wait for Change config Enable
		BCND	W_CCE,NTC			; bit to be set in GSR

		SPLK	#39,CANBCR2   		; BRP + 1 = 40

; bit 0-7	Baud rate prescaler	 
; bit 8-15	Reserved	

		SPLK	#0000000011111010b,CANBCR1   ; 50 kbps with 85 % sampling pt
;			 	 ||||||||||||||||            
;			 	 FEDCBA9876543210            

; bit 0-2	TSEG2	 
; bit 3-6	TSEG1				
; bit 7		Sample point setting (1: 3 times, 0: once)
; bit 8-9	Synchronization jump width 	
; bit A-F	Reserved 

		SPLK	#0000000000000000b,CANMCR 	
;			 	 ||||||||||||||||
;			 	 FEDCBA9876543210 

;bit 12		Change conf register

W_NCCE	BIT		CANGSR,#0Bh		; Wait for Change config disable
		BCND	W_NCCE,TC

;**************************************************************************
;***********                      TRANSMIT                       **********
;**************************************************************************
TX_LOOP	SPLK	#0080h,CANTCR	; Transmit request for mailbox 5
		
W_TA	BIT		CANTCR,BIT15	; Wait for transmission acknowledge
		BCND	W_TA,NTC

		SPLK	#8000h,CANTCR	; reset TA       		

;**************************************************************************
;***********                     RECEIVE                         **********
;**************************************************************************

W_RA	BIT		CANRCR,BIT4		; Wait for data from remote 
		BCND	W_RA,NTC		; node 
	
		SPLK	#0010h,CANRCR	; reset RMP and hence CANIFR   
		
; Check if transmitted and received data are same..

CHECK	MAR		*,AR5
		LACL	*+,AR0
		XOR		*+,AR6
		BCND	ERROR,NEQ
		BANZ	CHECK  
		CALL	AR_INIT

		MAR		*,AR7			; This loop merely keeps a 
		LACL	*				; count of the number of times
		ADD		#1				; data packets were transmitted
		SACL	*				; to the remote node.

		SETC	XF 				; A toggling XF bit indicates  
		RPT		#40h			; that the program is still 
		NOP						; running. This diagnostic aid
		CLRC	XF				; slows the traffic of CAN though	
			
LOOP	B		TX_LOOP			; Start all over again!  

ERROR	B		ERROR           ; Keep looping here in case of error..

;**************************************************************************
;***********		       COMMON ROUTINES  	         **********
;**************************************************************************

; AR Initializing routine

AR_INIT	LAR		AR0,#7204h		; AR0 => Mailbox 0 RAM (RECEIVE)
		LAR		AR5,#722Ch 		; AR5 => Mailbox 5 RAM (TRANSMIT)
	   	LAR		AR6,#03			; AR6 => Data Counter
		RET 

GISR1:	
GISR2:	
GISR3:	
GISR4:	
GISR5:	
GISR6:	
PHANTOM:	RET

		.end       
		
How filtering is achieved :
---------------------------
; Note: The CAN node in which this program is running is referred as "Xmitting" node

MSGID-MBX5: 0 1110 0001 0101 1101 1100 0011 0101 (Xmit MBX of Xmitting node)
MSGID-MBX0: 0 0111 0011 0101 1001 0100 0101 1001 (Rcv MBX of Receiving node)
      LAM0: 0 1101 1010 0010 1100 1000 1110 1101 (LAM0 of Receiving node)

; Note that wherever there is a zero in the LAM, the bits of the transmitted 
; MSGID and the MSGID of the Receive MBX are identical. The corresponding
; bits of transmit and receive MSGIDs could differ only if the corresponding
; LAM bit is a 1. The MSGID of the receive Mailbox is overwritten with the MSGID
; of the received message. Hence, filtering happens only for the first receive.

; Whenever the program on either node is terminated, the contents of memory
; location 300h should be the same (or +/- 1).

/* CANayzer config file: 50k80spRx.cfg */