ecrx0pol.asm

TI公司TMS320LF240X DSP实现CAN通讯的完整源代码！！！！！用2000系列DSP的同志不下载会后悔

* 		PROGRAM TO CHECK THE CAN OF 24X/240x DSP  						*
* 		ECRX0POL - Receive & Echo loop using Mailbox 0					*
* 	MBX0 used for RECEPTION		MBX5 used for TRANSMISSION				*
* This program RECEIVES & ECHOES data to another CAN module. 			*
* LPTX5POL program should be running on the other CAN module. This CAN  *
* module, after receiving the data packets, will echo the same data back*
* to the transmitting module which then verifies the Xmitted and Recvd  *
* data. The program loops forever.										*  

* COMMENTS : 
; This program, in conjunction with LPTX5POL, provides a quick and easy way
; to determine if two 24x/240x DSPs are able to communicate via the CAN bus. 
; This program does not use any interrupts and employs POLLING. Hence, it
; can be run anywhere in Program memory. 
; This program employs message filtering.
			  
	.title 		"ECRX0POL"  	; Title 
    .include    240x.h			; Variable and register declaration
	.include    "vector.h"		; Vector table (takes care of dummy password)
	.global		START

;------------------------------------------------------------------------
; Other constant definitions
;------------------------------------------------------------------------	 
DP_PF1		.set	0E0h	; Page 1 of peripheral file (7000h/80h)E0
DP_CAN		.set	0E2h    ; CAN Registers (7100h)
DP_CAN2		.set	0E4h   	; CAN RAM (7200h)

KICK_DOG	.macro				; Watchdog reset macro
		LDP		#00E0h
		SPLK	#05555h, WDKEY
		SPLK	#0AAAAh, WDKEY
		LDP		#0h
			.endm                 

		.text

START:	KICK_DOG                ; Reset Watchdog counter
		SPLK	#0,60h
		OUT		60h,WSGR		; Set waitstates for external memory (if used)
		SETC	INTM  			; Disable interrupts
		LDP		#DP_PF1		    ; Set PLL to x4 and
		SPLK	#0010h,SCSR1	; enable clock to CAN module
		SPLK	06Fh,WDCR		; Disable watchdog
		CALL	AR_INIT            
		LDP		#225		
		SPLK	#00C0H,MCRB		; Configure CAN pins	
			
		LAR		AR7,#300h		; AR7 keeps track of Receive cycles
		MAR		*,AR7
		SPLK	#0h,*

;**************************************************************************
;**************    Disable all mailboxes      ************************
;**************************************************************************

		LDP 	#DP_CAN    
		
		SPLK	#1000110110100010b,CANLAM0H 	; Set LAM (8DA2 C8ED)
		SPLK	#1100100011101101b,CANLAM0L		; 1:don't care
		
		SPLK	#0000000000000000b,CANMDER  	; Disable all mailboxes
;			 	 ||||||||||||||||	     		; Required before writing 
;			 	 FEDCBA9876543210	     		; to MSGID  
	                                
;**************************************************************************
;***********                Write CAN Mailboxes                  **********
;**************************************************************************
; Set MSGIDs for both transmit and receive mailboxes  

		LDP		#DP_CAN2
				
		SPLK	#1001011001011000b,CANMSGID5H	; Set mailbox 5 ID
;		  	 	 ||||||||||||||||			  	; XMIT Mailbox
;			 	 FEDCBA9876543210               ; 9658
 
        SPLK	#1101110101101011b,CANMSGID5L   ; DD6B
        
		SPLK	#1100011100110101b,CANMSGID0H	; Set mailbox 0 ID
;		  	 	 ||||||||||||||||				; RCV Mailbox
;			 	 FEDCBA9876543210               ; C735
  
        SPLK	#1001010001011001b,CANMSGID0L   ; 9459
		
		SPLK	#0000000000001000b,CANMSGCTRL5	; 0008
;			 	 ||||||||||||||||
;			 	 FEDCBA9876543210

;bit 0-3	Data length code. 1000 = 8 bytes
;bit 4		0: data frame
                  
;*******************************************************************
;******     ENABLE MBX AFTER WRITING TO MSGID/MSGCTRL     **********
;*******************************************************************

		LDP 	#DP_CAN
		SPLK	#0000000000100001b,CANMDER 	
;			 	 ||||||||||||||||
;			 	 FEDCBA9876543210

;bit 0-5	enable mailboxes 0 & 5

;*******************************************************************
;***********  Bit timing registers configuration    ****************
;*******************************************************************

		SPLK	#0001000000000000b,CANMCR 	
;			 	 ||||||||||||||||
;			 	 FEDCBA9876543210

;bit 12		Change configuration request for write-access to BCR (CCR=1)

W_CCE	BIT		CANGSR,#0Bh		; Wait for Change config Enable
		BCND	W_CCE,NTC		; bit to be set in GSR

		SPLK	#39,CANBCR2   		; BRP + 1 = 40

; bit 0-7	Baud rate prescaler	 
; bit 8-15	Reserved	

		SPLK	#0000000011111010b,CANBCR1   ; 50 kbps with 85 % sampling pt
;			 	 ||||||||||||||||            
;			 	 FEDCBA9876543210            

; bit 0-2	TSEG2	 
; bit 3-6	TSEG1				
; bit 7		Sample point setting (1: 3 times, 0: once)
; bit 8-9	Synchronization jump width 	
; bit A-F	Reserved 

		SPLK	#0000000000000000b,CANMCR 	
;			 	 ||||||||||||||||
;			 	 FEDCBA9876543210 

;bit 12		Change conf register

W_NCCE	BIT		CANGSR,#0Bh	; Wait for Change config disable
		BCND	W_NCCE,TC    

;**************************************************************************
;***********                     RECEIVE                         **********
;**************************************************************************
RX_LOOP:
W_RA	BIT		CANRCR,BIT4			; Wait for data from remote node
		BCND	W_RA,NTC    

		SPLK	#0010h,CANRCR		; reset RMP and hence CANIFR  
		
; Copy received data from MBX0 into MBX5 for transmission

COPY	MAR		*,AR0
		LACL	*+,AR5
		SACL	*+,AR6
		BANZ	COPY
		CALL	AR_INIT

		SPLK	#0080h,CANTCR		; Transmit request for mailbox 5
		
W_TA	BIT		CANTCR,BIT15		; Wait for transmission acknowledge
		BCND	W_TA,NTC

		SPLK	#8000h,CANTCR		; reset TA

        SETC	XF 					; A toggling XF bit indicates  
		RPT		#080h				; that the program is still 
		NOP							; running. 
		CLRC	XF				
		
		MAR		*,AR7				; This loop merely keeps a 
		LACL	*					; count of the number of times
		ADD		#1					; data packets were received
		SACL	*					; from the transmitting node.
LOOP	B		RX_LOOP	

;**************************************************************************
;***********		       COMMON ROUTINES  	         **********
;**************************************************************************

; AR Initializing routine

AR_INIT	LAR		AR0,#7204h		; AR0 => Mailbox 0 RAM (RECEIVE)
		LAR		AR5,#722Ch 		; AR5 => Mailbox 5 RAM (TRANSMIT)
	   	LAR		AR6,#03			; AR4 => Counter
		RET

GISR1:	
GISR2:	
GISR3:	
GISR4:	
GISR5:	
GISR6:	
PHANTOM:	RET

           .end 
           
/* CANayzer config file: 50k80spRx.cfg */