📄 fw.lst
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168 1
169 1 //set DYN_OUT=1, ENH_PKT=1
170 1 /*when DYN_OUT=0, the core automatically arms the endpoints when AUTOOUT is
171 1 switched from 0 to 1. This means that firmware must reset the endpoint
172 1 (and risk losing endpoint data) when switching between Auto-Out mode
173 1 and Manual-Out mode.When DYN_OUT=1, the core disables auto-arming of
174 1 the endpoints when AUTOOUT transitions from 0 to 1. This feature allows
175 1 CPU intervention when switching between AUTO and Manual mode without having to
176 1 reset the endpoint.
177 1 Note: When DYN_OUT=1 and AUTOOUT=1, the CPU is responsible for 'priming the pump'
178 1 by initially arming the endpoints (OUTPKTEND w/SKIP=1 to pass packets to host)
179 1 When ENH_PKT=0, the CPU can neither source OUT packets nor skip IN packets;
C51 COMPILER V6.10 FW 12/02/2005 23:12:52 PAGE 4
180 1 it has only the following capabilities:
181 1 OUT packets: Skip or Commit
182 1 IN packets: Commit or Edit/Source
183 1 When ENH_PKT=1, the CPU has additional capabilities:
184 1 OUT packets: Skip, Commit, or Edit/Source
185 1 IN packets: Skip, Commit, or Edit/Source*/
186 1
187 1 // REVCTL = 0x03;
188 1 // SYNCDELAY;
189 1 //Set FLAGS operate in INDEXed modes,
190 1
191 1 //FLAGA:'Programmable Full' flag for the FIFO indexed by FIFOADR[1:0]
192 1 //and FLAGB: 'Full Flag' for the FIFO indexed
193 1 PINFLAGSAB = 0x00;
194 1 SYNCDELAY;
195 1 //FLAGC: 'Empty flag' for the FIFO indexed
196 1 //and FLAGD : fixed as 'Programmable Full 'flag for EP2FIFO
197 1 PINFLAGSCD = 0x00;
198 1 SYNCDELAY;
199 1
200 1 //set FIFO flag pin polarity
201 1 //PKTEND,SLWR,SLRD,SLOE,EF,FF all are 'ACTIVE LOW'
202 1 FIFOPINPOLAR = 0x00;
203 1 SYNCDELAY;
204 1
205 1 // we are just using the default values, yes this is not necessary...
206 1 //Valid,DIR,TYPE[1:0],
207 1 EP2CFG = 0xA2; //Valid ,Out,Bulk,512size,Double buffer
208 1 SYNCDELAY;
209 1 EP6CFG = 0xE2; //Valid, In, Bulk,512size,double buffer
210 1 SYNCDELAY;
211 1 //RESET FIFOs(ep2 and ep6) Page340
212 1 FIFORESET =0x80; // activate NAK-ALL to avoid race conditions
213 1 SYNCDELAY;
214 1 FIFORESET =0x02;// reset, FIFO 2
215 1 SYNCDELAY;
216 1 FIFORESET =0x06;// reset, FIFO 6
217 1 SYNCDELAY;
218 1 FIFORESET =0x00;// deactivate NAK-ALL
219 1 SYNCDELAY;
220 1
221 1 //set EP2 width to 8bit;
222 1 EP2FIFOCFG &=0xfe;
223 1 SYNCDELAY;
224 1
225 1 //set EP4 width to 8bit;
226 1 EP4FIFOCFG &=0xfe;
227 1 SYNCDELAY;
228 1
229 1 //set EP6 width to 8bit
230 1 EP6FIFOCFG &=0xfe;
231 1 SYNCDELAY;
232 1
233 1 //set FLAGB one sample earlier
234 1 EP6FIFOCFG |=0x40;
235 1 SYNCDELAY;
236 1
237 1 //Enable ZERO packet
238 1 EP6FIFOCFG |=0x04;
239 1 SYNCDELAY;
240 1
241 1 //Enable EP6 AUTOIN
C51 COMPILER V6.10 FW 12/02/2005 23:12:52 PAGE 5
242 1 EP6FIFOCFG |=0x08;
243 1 SYNCDELAY;
244 1
245 1 //set EP8 width to 8bit
246 1 EP8FIFOCFG &=0xfe;
247 1 SYNCDELAY;
248 1
249 1 //set FD8:15 as output
250 1 OED=0xff;
251 1
252 1 //Drive FD15 High
253 1 IOD=0x80;
254 1
255 1 //EPx AUTOIN packet length: 0x0200 in HighSped mode, and 0x0040 in fullspeed mode
256 1 //These register can be used to set smaller packet sizes than the physical buffer size
257 1 EP6AUTOINLENH = 0x00; // set core AUTO commit len = 64 bytes
258 1 SYNCDELAY; //
259 1 EP6AUTOINLENL = 0x40;
260 1 SYNCDELAY; //
261 1
262 1 //For CPU mode,using this method to arm both Ep2 buffers
263 1 EP2BCL = 0x80; // arm EP2OUT by writing byte count w/skip.
264 1 SYNCDELAY;
265 1 EP2BCL = 0x80;
266 1 SYNCDELAY;
267 1
268 1 //set programmable Full Flag
269 1 //EPxFIFOPFH and EPxFIFOPFL
270 1
271 1
272 1 // The following section of code is used to relocate the descriptor table.
273 1 // Since the SUDPTRH and SUDPTRL are assigned the address of the descriptor
274 1 // table, the descriptor table must be located in on-part memory.
275 1 // The 4K demo tools locate all code sections in external memory.
276 1 // The descriptor table is relocated by the frameworks ONLY if it is found
277 1 // to be located in external memory.
278 1 pDeviceDscr = (WORD)&DeviceDscr;
279 1 pDeviceQualDscr = (WORD)&DeviceQualDscr;
280 1 pHighSpeedConfigDscr = (WORD)&HighSpeedConfigDscr;
281 1 pFullSpeedConfigDscr = (WORD)&FullSpeedConfigDscr;
282 1 pStringDscr = (WORD)&StringDscr;
283 1
284 1 if ((WORD)&DeviceDscr & 0xe000)
285 1 {
286 2 IntDescrAddr = INTERNAL_DSCR_ADDR;
287 2 ExtDescrAddr = (WORD)&DeviceDscr;
288 2 DevDescrLen = (WORD)&UserDscr - (WORD)&DeviceDscr + 2;
289 2 for (i = 0; i < DevDescrLen; i++)
290 2 *((BYTE xdata *)IntDescrAddr+i) = 0xCD;
291 2 for (i = 0; i < DevDescrLen; i++)
292 2 *((BYTE xdata *)IntDescrAddr+i) = *((BYTE xdata *)ExtDescrAddr+i);
293 2 pDeviceDscr = IntDescrAddr;
294 2 offset = (WORD)&DeviceDscr - INTERNAL_DSCR_ADDR;
295 2 pDeviceQualDscr -= offset;
296 2 pConfigDscr -= offset;
297 2 pOtherConfigDscr -= offset;
298 2 pHighSpeedConfigDscr -= offset;
299 2 pFullSpeedConfigDscr -= offset;
300 2 pStringDscr -= offset;
301 2 }
302 1
303 1 EA = 0; // Diable 8051 interrupts
C51 COMPILER V6.10 FW 12/02/2005 23:12:52 PAGE 6
304 1
305 1 CKCON = (CKCON&(~bmSTRETCH)) | FW_STRETCH_VALUE; // Set stretch to 0 (after renumeration)
306 1
307 1 // clear the Sleep flag.
308 1 Sleep = FALSE;
309 1
310 1 //Write DS1073 MUX
311 1 WRITE_DS1073();
312 1 //output pa0=1,the relay on
313 1 IOA |=0x01;
314 1 //Power OFF LM2941
315 1 IOA |=0x02;
316 1 EZUSB_Delay(1000);
317 1 //Power ON LM2941
318 1 IOA &=0xfd;
319 1
320 1 while(1)
321 1 {
322 2 TD_Poll();
323 2 }
324 1 }
325
MODULE INFORMATION: STATIC OVERLAYABLE
CODE SIZE = 579 ----
CONSTANT SIZE = 10 ----
XDATA SIZE = ---- ----
PDATA SIZE = ---- ----
DATA SIZE = 14 16
IDATA SIZE = ---- ----
BIT SIZE = 4 ----
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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