📄 cshrd.h
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//
#define CRYSTAL_TCR_LINK_OFF ((USHORT)(0x0080))
#define CRYSTAL_TCR_ENDEC_LOOPBACK ((USHORT)(0x0200))
#define CRYSTAL_TCR_AUI_LOOPBACK ((USHORT)(0x0400))
#define CRYSTAL_TCR_BACKOFF_OFF ((USHORT)(0x0800))
#define CRYSTAL_TCR_FULL_DUPLEX_ON ((USHORT)(0x4000))
#define CRYSTAL_TCR_FAST_TEST ((USHORT)(0x8000))
//
// Receive Event Bit definition
// Read-only
//
#define CRYSTAL_RER_IA_HASHED ((USHORT)(0x0040))
#define CRYSTAL_RER_DRIBBLE ((USHORT)(0x0080))
#define CRYSTAL_RER_PACKET_RECEIVED_OK ((USHORT)(0x0100))
#define CRYSTAL_RER_HASHED_RECEIVED ((USHORT)(0x0200))
#define CRYSTAL_RER_INDIVIDUAL_RECEIVED ((USHORT)(0x0400))
#define CRYSTAL_RER_BROADCAST_RECEIVED ((USHORT)(0x0800))
#define CRYSTAL_RER_CRC_ERROR ((USHORT)(0x1000))
#define CRYSTAL_RER_RUNT ((USHORT)(0x2000))
#define CRYSTAL_RER_EXTRA_DATA ((USHORT)(0x4000))
#define CRYSTAL_RER_HASH_INDEX_MASK ((USHORT)(0xFC00))
//
// Transmit Event Bit definition
// Read-only
//
#define CRYSTAL_TER_LOST_CRS ((USHORT)(0x0040))
#define CRYSTAL_TER_SQE_ERROR ((USHORT)(0x0080))
#define CRYSTAL_TER_PACKET_TRANSMITTED_OK ((USHORT)(0x0100))
#define CRYSTAL_TER_OUT_OF_WINDOW ((USHORT)(0x0200))
#define CRYSTAL_TER_JABBER ((USHORT)(0x0400))
#define CRYSTAL_TER_EXCESSIVE_COLLISIONS ((USHORT)(0x8000))
#define CRYSTAL_TER_COLLISIONS_MASK ((USHORT)(0x7800))
#define CRYSTAL_TER_COLLISIONS_SHIFT ((USHORT)(0x000B))
//
// Buffer Event Bit definition
// Read-only
//
#define CRYSTAL_BER_SW_INTERRUPT ((USHORT)(0x0040))
#define CRYSTAL_BER_RX_DMA ((USHORT)(0x0080))
#define CRYSTAL_BER_READY_FOR_TRANSMIT ((USHORT)(0x0100))
#define CRYSTAL_BER_TX_UNDERRUN ((USHORT)(0x0200))
#define CRYSTAL_BER_RX_MISS ((USHORT)(0x0400))
#define CRYSTAL_BER_RX_128_BYTE ((USHORT)(0x0800))
#define CRYSTAL_BER_TX_COL_OVERRFLOW ((USHORT)(0x1000))
#define CRYSTAL_BER_RX_MISS_OVERFLOW ((USHORT)(0x2000))
#define CRYSTAL_BER_RX_DESTINATION_MATCH ((USHORT)(0x8000))
//
// Ethernet Line Status bit definition
// Read-only
//
#define CRYSTAL_LSR_LINK_OK ((USHORT)(0x0080))
#define CRYSTAL_LSR_AUI_ON ((USHORT)(0x0100))
#define CRYSTAL_LSR_TENBASET_ON ((USHORT)(0x0200))
#define CRYSTAL_LSR_NWAY_FDX ((USHORT)(0x0400))
#define CRYSTAL_LSR_NWAY_ACTIVE ((USHORT)(0x0800))
#define CRYSTAL_LSR_POLARITY_OK ((USHORT)(0x1000))
#define CRYSTAL_LSR_CRS_OK ((USHORT)(0x4000))
//
// Chip Software Status bit definition
// Read-only
//
#define CRYSTAL_SSR_ACTIVE_33V ((USHORT)(0x0040))
#define CRYSTAL_SSR_INIT_DONE ((USHORT)(0x0080))
#define CRYSTAL_SSR_SI_BUSY ((USHORT)(0x0100))
#define CRYSTAL_SSR_EEPROM_PRESENT ((USHORT)(0x0200))
#define CRYSTAL_SSR_EEPROM_OK ((USHORT)(0x0400))
#define CRYSTAL_SSR_EL_PRESENT ((USHORT)(0x0800))
#define CRYSTAL_SSR_EE_SIZE_64 ((USHORT)(0x1000))
//
// ISA Bus Status bit definition
// Read-only
//
#define CRYSTAL_BSR_TX_BID_ERROR ((USHORT)(0x0080))
#define CRYSTAL_BSR_READY_FOR_TRANSMIT_NOW ((USHORT)(0x0100))
//
// The following block defines the ISQ event types
//
#define CRYSTAL_ISQ_RECEIVE_EVENT ((USHORT)(0x0004))
#define CRYSTAL_ISQ_TRANSMIT_EVENT ((USHORT)(0x0008))
#define CRYSTAL_ISQ_BUFFER_EVENT ((USHORT)(0x000c))
#define CRYSTAL_ISQ_RECEIVE_MISS_OVERFLOW_EVENT ((USHORT)(0x0010))
#define CRYSTAL_ISQ_TX_COL_OVERFLOW_EVENT ((USHORT)(0x0012))
#define CRYSTAL_ISQ_EVENT_MASK ((USHORT)(0x003F))
#define CRYSTAL_REG_NUMBER_MASK ((USHORT)(0x003F))
#define CRYSTAL_REG_NUMBER_TX_CMD ((USHORT)(0x0009))
//
// Mask value for Address Auto-Increment.
//
#define CRYSTAL_ENABLE_AUTO_INCREMENT ((USHORT)(0x8000))
#define CRYSTAL_MAX_MULTICAST_ENTRIES 64
#define CRYSTAL_ADAPTER_TYPE_ISA 0
#define CS89XX_ISA_ID_LOW 0x630e
#define CS89XX_ISA_ID_HI 0
//
// Dmaed Frame Structure
//
typedef struct _CRYSTAL_DMA_FRAME {
USHORT RxFrameStatus;
USHORT RxFrameSize;
}CRYSTAL_DMA_FRAME,*PCRYSTAL_DMA_FRAME;
#define CRYSTAL_DMA_16K 16*1024
#define CRYSTAL_DMA_64K 64*1024
#define CRYSTAL_BOUNDARY_128K 128*1024
#define CRYSTAL_DMA_ALIGN_VALUE 0x010000
#define CRYSTAL_BOUNDARY_16M (1024*1024*16)
#define CRYSTAL_DMA_ALLIGN_MASK 0x0FFFF
#define CRYSTAL_FRAME_OFFSET_DMA_MASK CRYSTAL_DMA_16K-1
#define CRYSTAL_DMA_FRAME_COUNT_MASK 0x0FFF
#define DMA_HIGHEST_ACCEPTABLE_MEMORY_LOW 0x1000000
#define DMA_HIGHEST_ACCEPTABLE_MEMORY_HI (0x00)
//------------------------------------------------------------------------------+
// Dma Details |
//------------------------------------------------------------------------------+
#define DMA_16MASK_REG 0xD4
#define DMA_16MODE_REG 0xD6
#define CIRCULAR_MODE 0x14
#define DMA_CLEAR_FLIPFLOP 0xD8
#define DMA_CHANNEL_FIELD 0x03
#define SET_DMA_MASK 0x04
#define CRYSTAL_SCAN_SIGNATURE 0x3000
#define CRYSTAL_SCAN_MASK 0xF000
#define BAD_EEPROM 0xFFFF
#define MAXLOOP 0x8888
#define EEPROM_READ_REGISTER ((USHORT)(0x0200))
#define EE_ADDRESS_OEM_IA_W1 ((USHORT)(0x001C)) //48-bits FFFFEEEEDDDD
#define EE_ADDRESS_OEM_IA_W2 ((USHORT)(0x001D))
#define EE_ADDRESS_OEM_IA_W3 ((USHORT)(0x001E))
#define EE_ADDRESS_FLAGS ((USHORT)(0x001F))
#define EE_ADDRESS_MEM_BASE ((USHORT)(0x0020)) // MMM0 MemBase 12-bits
//MMM000 23-12 in 24-bit
//ISA address space
#define EE_ADDRESS_BOOT_BASE ((USHORT)(0x0021)) //BBB0 BootBase 12-bits
//BBB000 23-12 in 24-bit
//ISA address space
#define EE_ADDRESS_BOOT_MASK ((USHORT)(0x0022)) //FFF0 BootMask 12-bits
// FFF000 23-12 in 24-bit
//ISA address space
#define EE_ADDRESS_CTL ((USHORT)(0x0023)) //0N0B NwayCTL and Bus CTL
#define EE_ADDRESS_VRHC ((USHORT)(0x0024)) //Version 4-bits V 2-Rattler
// 1-Sparrow
#define EE_ADDRESS_SOFT ((USHORT)(0x0025)) //SOFT Software 16-bits of
//non-volatile software info
#define EE_SERIAL_NUMBER_HIGH ((USHORT)(0x0032)) //Serial High
#define EE_SERIAL_NUMBER_LOW ((USHORT)(0x0033)) //Serial Low
#define EE_ADDRESS_BOARD ((USHORT)(0x0026)) //Board specific info
#define EE_ADDRESS_PROD_ID ((USHORT)(0x0026)) // Product ID
#define EE_ADDRESS_DATE ((USHORT)(0x0027)) // Mfg date
#define EE_ADDRESS_MFG_IA_W1 ((USHORT)(0x0028)) //FFFF Mfg IA
#define EE_ADDRESS_MFG_IA_W2 ((USHORT)(0x0029)) //48-bits FFFFEEEEDDDD
#define EE_ADDRESS_MFG_IA_W3 ((USHORT)(0x002A))
#define EE_ADDRESS_EISA_ID_W1 ((USHORT)(0x002B)) // 32-bits E3E2E1E0
#define EE_ADDRESS_EISA_ID_W2 ((USHORT)(0x002C))
#define EE_ADDRESS_RESERVED_W1 ((USHORT)(0x002D))
#define EE_ADDRESS_RESERVED_W2 ((USHORT)(0x002E)) // Reserved, checksummed
//Flags in EEPROM for our use
#define EE_MEM_FLAG ((USHORT)(0x8000))
#define EE_BOOT_PROM_FLAG ((USHORT)(0x4000))
#define EE_DMA_DISABLE ((USHORT)(0x30 ))
#define EE_IRQ_FLAG ((USHORT)(0x1000))
#define EE_DMA_ADJUST ((USHORT)(0x4 ))
#define EE_DMA_MASK ((USHORT)(0x0070)) //To extract the dma channel number
#define EE_DMA_ONLY ((USHORT)(0x0800)) //EEPROM RX Cfg Bit for DMA only
#define EE_AUTO_DMA ((USHORT)(0x0400)) //EEPROM RX Cfg Bit for Auto DMA
#define EE_DMA_BURST_ENBL ((USHORT)(0x1000))
#define EE_BUS_CTL_MASK ((USHORT)(0x000F)) // Configuration for bus CTL
#define EE_LINE_CTL_MASK ((USHORT)(0x0F00)) // Configuration for bus CTL
#define EE_INTERRUPT_MASK ((USHORT)(0x000F))
#define EE_MEMORY_MASK ((USHORT)(0xFFF0))
#define EE_IOCHRDY_ENBL ((USHORT)(0x100 ))
#define EE_USE_SA ((USHORT)(0x80 ))
#define EE_STREAM_TRANSFER ((USHORT)(0x2000))
#define EE_MEM_BASE_ADJUST 8
#define AUTO_NEG_MASK ((USHORT)(0x8380))
#define EE_MEDIA_MASK ((USHORT)(0x0060))
#define EE_LOAD_WITHOUT_CABLE ((USHORT)(0x0040))
#define EE_MEDIA_SHIFT 5
#define EE_AUTODETECT 0
#define EE_10BASET 1
#define EE_AUI 2
#define EE_BNC 3
#define EE_LA_DECODE_CKT 4
#define EE_HW_STANDBY 5
#define EE_RX_DMA_SIZE ((USHORT)(0x200 ))
#define EE_CKT_MASK ((USHORT)(0x07 ))
#define EE_10BASET_CKT 1
#define EE_AUI_CKT 2
#define EE_BNC_CKT 4
#define EE_FORCE_FDX ((USHORT)(0x8000))
#define EE_NLP_ENABLE ((USHORT)(0x0200))
#define EE_AUTONEG_ENABLE ((USHORT)(0x0100))
#define EE_ALLOW_FDX ((USHORT)(0x0080))
#define EE_WAKEUP_CAPEABLE ((USHORT)(0x0400))
#define EE_WAKEUP_CONFIGURED ((USHORT)(0x0200))
#define EE_WAKEUP_ENABLED ((USHORT)(0x0100))
#define EE_DCDC_POLARITY ((USHORT)(0x0080))
#endif _CRYSTALHARDWARE_
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