📄 cshrd.h
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typedef struct _CRYSTAL_PACKET_PAGE {
ULONG CrystalChipEisaId; // offset 0-> Corp -ID
UCHAR Reserved[16];
USHORT CrystalIsaIoBaseAddress; // offset 20h
USHORT CrystalIsaInterruptNumber; // offset 22h
USHORT CrystalIsaDmaChannel; // offset 24h
USHORT CrystalIsaDmaStartOfFrameOffset; // offset 26h
USHORT CrystalIsaDmaFrameCount; // offset 28h
USHORT CrystalIsaDmaByteCount; // offset 2Ah
ULONG CrystalIsaMemoryBaseAddress; // offset 2Ch
ULONG CrystalBootPromBaseAddress; // offset 30h
ULONG CrystalBootPromAddressMask; // offset 34h
UCHAR Reserved1[8]; // Reserved
USHORT CrystalEepromDataWord; // offset 40h
USHORT CrystalEepromOpCode; // offset 42h
UCHAR Reserved2[0x102-0x44]; // Filler
USHORT CrystalRxConfigRegister; // offset 102h
USHORT CrystalRxControlRegister; // offset 104h
USHORT CrystalTxConfigRegister; // offset 106h
USHORT CrystalTxCommandRegister; // offset 108h
USHORT CrystalBufferConfigRegister; // offset 10Ah
UCHAR Reserved3[6];
USHORT CrystalLineControlRegister; // offset 112h
USHORT CrystalSelfControlRegister; // offset 114h
USHORT CrystalBusControlRegister; // offset 116h
USHORT CrystalTestControlRegister; // offset 118h
USHORT CrystalInterruptStatusQueue; // offset 120h
UCHAR Reserved5[2];
USHORT CrystalRxEventRegister; // offset 124h
UCHAR Reserved6[2];
USHORT CrystalTxEventRegister; // offset 128h
UCHAR Reserved7[2];
USHORT CrystalBufEventRegister; // offset 12Ch
UCHAR Reserved8[2];
USHORT CrystalRxMissCount; // offset 130h
USHORT CrystalTxColCount; // offset 132h
USHORT CrystalLineStatusRegister; // offset 134h
USHORT CrystalSelfStatusRegister; // offset 136h
USHORT CrystalBusStatusRegister; // offset 138h
UCHAR Reserved9[2];
USHORT CrystalTdrRegister; // offset 13Ch
UCHAR Reserved10[2];
UCHAR Reserved11[2];
UCHAR Reserved12[2];
USHORT CrystalTransmitCommand; // offset 144h
USHORT CrystalTransmitLength; // offset 146h
UCHAR Reserved13[8];
USHORT CrystalLogicalAddressFilter[4]; // offset 150h
UCHAR CrystalIndividualAddress[8]; // offset 158h
UCHAR Reserved14[672];
USHORT CrystalReceiveStatus; // offset 400h
USHORT CrystalReceiveLength; // offset 402h
UCHAR CrystalReceiveFramePtr[0x0A00-0x0404]; // offset 404h
UCHAR CrystalTransmitFramePtr; // offset A00h
} CRYSTAL_PACKET_PAGE,*PCRYSTAL_PACKET_PAGE;
//
// End of Packet Page Structure.
//
// @kml 6/29/99
//#define CRYSTAL_AUTONEG_DEFAULT_VALUE NLP_ENABLE;
//#define CRYSTAL_AUTONEG_UNDEFINED 0xffff
// Defines Control/Config register quintuplet numbers
//
#define RX_BUF_CFG ((USHORT)(0x0003))
#define RX_CONTROL ((USHORT)(0x0005))
#define TX_CFG ((USHORT)(0x0007))
#define TX_COMMAND ((USHORT)(0x0009))
#define BUF_CFG ((USHORT)(0x000B))
#define LINE_CONTROL ((USHORT)(0x0013))
#define SELF_CONTROL ((USHORT)(0x0015))
#define BUS_CONTROL ((USHORT)(0x0017))
#define TEST_CONTROL ((USHORT)(0x0019))
//
// Defines Status/Count registers quintuplet numbers
//
#define RX_EVENT ((USHORT)(0x0004))
#define TX_EVENT ((USHORT)(0x0008))
#define BUF_EVENT ((USHORT)(0x000C))
#define RX_MISS_COUNT ((USHORT)(0x0010))
#define TX_COL_COUNT ((USHORT)(0x0012))
#define LINE_STATUS ((USHORT)(0x0014))
#define SELF_STATUS ((USHORT)(0x0016))
#define BUS_STATUS ((USHORT)(0x0018))
#define TDR ((USHORT)(0x001C))
//
// Receive Configuration and Interrupt Mask bit definition
// Read/write
#define CRYSTAL_RCR_SKIP_1 ((USHORT)(0x0040))
#define CRYSTAL_RCR_RX_STREAM_ENABLE ((USHORT)(0x0080))
#define CRYSTAL_RCR_RX_OK_ENABLE ((USHORT)(0x0100))
#define CRYSTAL_RCR_DMA_ONLY ((USHORT)(0x0200))
#define CRYSTAL_RCR_AUTO_RX_DMA ((USHORT)(0x0400))
#define CRYSTAL_RCR_BUFFER_CRC ((USHORT)(0x0800))
#define CRYSTAL_RCR_RX_CRC_ERROR_ENABLE ((USHORT)(0x1000))
#define CRYSTAL_RCR_RX_RUNT_ENABLE ((USHORT)(0x2000))
#define CRYSTAL_RCR_RX_EXTRA_DATA_ENABLE ((USHORT)(0x4000))
#define CRYSTAL_DEFAULT_RX_CONFIG_VALUE ((USHORT)\
(CRYSTAL_RCR_RX_CRC_ERROR_ENABLE|\
CRYSTAL_RCR_RX_OK_ENABLE|\
CRYSTAL_RCR_RX_RUNT_ENABLE|\
CRYSTAL_RCR_RX_EXTRA_DATA_ENABLE|\
CRYSTAL_RCR_BUFFER_CRC))
//
// Receive Control bit definition
// Read/write
//
#define CRYSTAL_RCR_RX_IA_HASH_ACCEPT ((USHORT)(0x0040))
#define CRYSTAL_RCR_RX_PROM_ACCEPT ((USHORT)(0x0080))
#define CRYSTAL_RCR_RX_OK_ACCEPT ((USHORT)(0x0100))
#define CRYSTAL_RCR_RX_MULTICAST_ACCEPT ((USHORT)(0x0200))
#define CRYSTAL_RCR_RX_IA_ACCEPT ((USHORT)(0x0400))
#define CRYSTAL_RCR_RX_BROADCAST_ACCEPT ((USHORT)(0x0800))
#define CRYSTAL_RCR_RX_BAD_CRC_ACCEPT ((USHORT)(0x1000))
#define CRYSTAL_RCR_RX_RUNT_ACCEPT ((USHORT)(0x2000))
#define CRYSTAL_RCR_RX_EXTRA_DATA_ACCEPT ((USHORT)(0x4000))
#define CRYSTAL_RCR_DEFAULT_VALUE ((USHORT)(CRYSTAL_RCR_RX_OK_ACCEPT))
// #define CRYSTAL_RCR_DEFAULT_VALUE ((USHORT)(CRYSTAL_RCR_RX_OK_ACCEPT | \
// CRYSTAL_RCR_RX_BAD_CRC_ACCEPT | \
// CRYSTAL_RCR_RX_RUNT_ACCEPT | \
// CRYSTAL_RCR_RX_EXTRA_DATA_ACCEPT))
//
// Transmit Configuration Interrupt Mask bit definition
// Read/write
//
#define CRYSTAL_TCR_TX_LOST_CRS_ENABLE ((USHORT)(0x0040))
#define CRYSTAL_TCR_TX_SQE_ERROR_ENABLE ((USHORT)(0x0080))
#define CRYSTAL_TCR_TX_OK_ENABLE ((USHORT)(0x0100))
#define CRYSTAL_TCR_TX_LATE_COLLISION_ENABLE ((USHORT)(0x0200))
#define CRYSTAL_TCR_TX_JABBER_ENABLE ((USHORT)(0x0400))
#define CRYSTAL_TCR_TX_ANY_COL_ENABLE ((USHORT)(0x0800))
#define CRYSTAL_TCR_TX_16_COL_ENABLE ((USHORT)(0x8000))
#define CRYSTAL_TCR_DEFAULT_VALUE ((USHORT)\
CRYSTAL_TCR_TX_LOST_CRS_ENABLE|\
CRYSTAL_TCR_TX_OK_ENABLE|\
CRYSTAL_TCR_TX_LATE_COLLISION_ENABLE|\
CRYSTAL_TCR_TX_JABBER_ENABLE|\
CRYSTAL_TCR_TX_16_COL_ENABLE)
// Transmit Command bit definition
// Read-only
//
#define CRYSTAL_TCR_TX_START_5_BYTES ((USHORT)(0x0000))
#define CRYSTAL_TCR_TX_START_381_BYTES ((USHORT)(0x0040))
#define CRYSTAL_TCR_TX_START_1021_BYTES ((USHORT)(0x0080))
#define CRYSTAL_TCR_TX_START_ALL_BYTES ((USHORT)(0x00C0))
#define CRYSTAL_TCR_TX_FORCE ((USHORT)(0x0100))
#define CRYSTAL_TCR_TX_ONE_COLLISION ((USHORT)(0x0200))
#define CRYSTAL_TCR_TX_TWO_PART_DEFF_DISABLE ((USHORT)(0x0400))
#define CRYSTAL_TCR_TX_NO_CRC ((USHORT)(0x1000))
#define CRYSTAL_TCR_TX_PAD_DISABLE ((USHORT)(0x2000))
//
// Buffer Configuration Interrupt Mask bit definition
// Read/write
//
#define CRYSTAL_BCR_GENERATE_SW_INTERRUPT ((USHORT)(0x0040))
#define CRYSTAL_BCR_RX_DMA_ENABLE ((USHORT)(0x0080))
#define CRYSTAL_BCR_READY_FOR_TX_ENABLE ((USHORT)(0x0100))
#define CRYSTAL_BCR_TX_UNDERRUN_ENABLE ((USHORT)(0x0200))
#define CRYSTAL_BCR_RX_MISS_ENABLE ((USHORT)(0x0400))
#define CRYSTAL_BCR_RX_128_BYTE_ENABLE ((USHORT)(0x0800))
#define CRYSTAL_BCR_TX_COL_COUNT_OVRFLOW_ENABLE ((USHORT)(0x1000))
#define CRYSTAL_BCR_RX_MISS_COUNT_OVRFLOW_ENABLE ((USHORT)(0x2000))
#define CRYSTAL_BCR_RX_DEST_MATCH_ENABLE ((USHORT)(0x8000))
//@drsc 3.21 add CS8900 support
#define CRYSTAL_BCR_DEFAULT_VALUE ((USHORT)\
CRYSTAL_BCR_TX_UNDERRUN_ENABLE|\
CRYSTAL_BCR_TX_COL_COUNT_OVRFLOW_ENABLE|\
CRYSTAL_BCR_RX_MISS_COUNT_OVRFLOW_ENABLE|\
CRYSTAL_BCR_READY_FOR_TX_ENABLE)
//
// Line Control bit definition
// Read/write
//
#define CRYSTAL_LCR_SERIAL_RX_ON ((USHORT)(0x0040))
#define CRYSTAL_LCR_SERIAL_TX_ON ((USHORT)(0x0080))
#define CRYSTAL_LCR_AUI_ONLY ((USHORT)(0x0100))
#define CRYSTAL_LCR_AUTO_AUI_10BASET ((USHORT)(0x0200))
#define CRYSTAL_LCR_NWAY_ENABLE ((USHORT)(0x0400))
#define CRYSTAL_LCR_MODIFIED_BACKOFF ((USHORT)(0x0800))
#define CRYSTAL_LCR_AUTO_CORRECT_POLARITY ((USHORT)(0x1000))
#define CRYSTAL_LCR_LOW_RX_SQUELCH ((USHORT)(0x4000))
#define CRYSTAL_LCR_NWAY_PULSES ((USHORT)(0x8000))
//@203
#define CRYSTAL_LCR_WAKE_ENABLE ((USHORT)(0x8000))
#define CRYSTAL_LCR_DEFAULT_VALUE ((USHORT)(0))
//
// Software Self Control bit definition
// Read/write
//
#define CRYSTAL_SCR_POWER_ON_RESET ((USHORT)(0x0040))
#define CRYSTAL_SCR_SW_SUSPEND ((USHORT)(0x0100))
#define CRYSTAL_SCR_HW_SLEEP_ENABLE ((USHORT)(0x0200))
#define CRYSTAL_SCR_HW_STANDBY_ENABLE ((USHORT)(0x0400))
#define CRYSTAL_SCR_HCO_0_ENABLE ((USHORT)(0x1000))
#define CRYSTAL_SCR_HCO_1_ENABLE ((USHORT)(0x2000))
#define CRYSTAL_SCR_HCO_0 ((USHORT)(0x4000))
#define CRYSTAL_SCR_HCO_1 ((USHORT)(0x8000))
//
// ISA Bus Control bit definition
// Read/write
//
#define CRYSTAL_BCR_RESET_RX_DMA ((USHORT)(0x0040))
#define CRYSTAL_BCR_USE_SA ((USHORT)(0x0200))
#define CRYSTAL_BCR_MEMORY_ON ((USHORT)(0x0400))
#define CRYSTAL_BCR_DMA_BURST ((USHORT)(0x0800))
#define CRYSTAL_BCR_IO_CHANNEL_READY_ON ((USHORT)(0x1000))
#define CRYSTAL_BCR_RX_DMA_SIZE_64K ((USHORT)(0x2000))
#define CRYSTAL_BCR_INTERRUPT_ENABLE ((USHORT)(0x8000))
#define CRYSTAL_BUS_DEFAULT_VALUE CRYSTAL_BCR_INTERRUPT_ENABLE
//
// Test Control bit definition
// Read/write
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